issues within the context of traditional scaled-silicon systems and to find alternatives that circumvent the approaching barriers. Of great interest has been the field of nanotechnology, where multiple materials are innovatively positioned with nanometer precision.

The ITRS, discussed in Chapter 2, is industry’s best analysis of all factors (fabrication, interconnects, thermal management, cross talk, cost, packaging, etc.) that must be considered in order to continue the miniaturization progress. The ITRS identifies a number of “brick walls”—major technology issues for which there is no known solution—as well other important technological challenges for which promising approaches have been identified. Given the current state of knowledge of CMOS and of the alternatives as they are now understood, the best guess for the next 10-15 years is that silicon CMOS technology will continue to provide the fastest switching time at the lowest cost in the smallest gate with the most cost-effective system integration.

The continuing hegemony of CMOS devices and circuits is based on substantial improvements and the introduction of highly innovative ideas. At the 2001 International Electron Devices Meeting, Intel announced a transistor operating at 3.3 terahertz.4 At this same meeting, Advanced Micro Devices (AMD) announced that variations on CMOS transistors operate with 15-nm feature sizes. A November 26, 2001, announcement by Intel disclosed a “depleted substrate transistor” having a leakage current 100 times smaller than present transistors and, therefore, a 104 smaller gate leakage power.5 This innovation could contribute substantially to the alleviation of heat dissipation that currently looms as a major issue. Other conventional approaches promote the use of asynchronous design or self-timed circuits operating without a single, chipwide clock speed orchestrating the tempo of each transistor.6 CMOS and its many variations represent opportunities for vast improvements as nanoscale dimensions are reached.

Nonetheless, there are ultimate barriers to continued CMOS scaling, and new approaches for new devices and functions are being explored. Quantum interference effects, for example, may provide opportunities for new devices and functions. Some of the new approaches are based on alternative designs for transistors, while others represent entirely new ideas for logic operations. It is clear that the current architecture for digital computers is not unique, nor does it provide the greatest capability for some operations. The brain is able to process information for operations such as image recognition with far greater speed and efficacy than current computational approaches. Just how alternative architectures may operate, and which ones are likely to provide substantial improvement for certain operations, remains a frontier of current research.

There have been many attempts to think outside the box. Radically different approaches are being investigated that, in most cases, attack only one small element of what, ultimately, must be an integrated effort tying together many factors that must be satisfied simultaneously for such a system to be of practical use (in a manner similar to the ITRS). These new approaches, some of which

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