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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium Moore’s Law and the Economics of Semiconductor Price Trends Kenneth Flamm University of Texas at Austin In 1965, just 5 years after the construction of the first integrated circuit (IC), Gordon E. Moore (then at Fairchild Semiconductor) predicted that the number of devices on a single integrated circuit would double every year.1 Later modifications of that early prediction have passed into the everyday jargon of our hightech society as “Moore’s Law.” Moore’s Law is nowadays invoked to explain just about anything pertaining to high technology: the explosion in Internet use of the late 1990s: rapid improvement in price-performance in semiconductors, computers, communications, and just about everything electronic; the continuing rapid improvement in the technical capabilities of information technology; and the productivity rebound of the late 1990s in the U.S. economy. All of these things, indeed, may be connected to Moore’s Law, but “explaining” them with a reference to Moore’s Law may obscure more than it illuminates. This paper creates a framework for interpreting the economic implications of Moore’s Law. I first describe the history of Moore’s Law predictions and explain why they have such potentially wide-ranging consequences. I then show how a Moore’s Law prediction must be coupled with other assumptions in order to produce an economically meaningful link to what is the key economic variable of the information age: the cost or price of electronic functionality, as implemented in a semiconductor integrated circuit. I then relate the historical evolution of semiconductor prices through the mid-1990s to developments in several key parameters 1 I am grateful for useful conversations about some of the ideas in this paper with Alan Allen, Denis Fandel, Dale Jorgenson, Paul Landler, Bill Spencer, and Phillip Webre. Responsibility for the errors is mine alone.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium TABLE 1 Changing Size: U.S. Semiconductor Manufacturing Value Added vs. GDP Year Percent of GDP 1958 0.04 1965 0.09 1975 0.13 1985 0.26 1995 0.70 1997 0.77 SOURCE: U.S. Census of Manufactures, Bureau of Economic Analysis, U.S. Department of Commerce. over this historical period. I then link acceleration in the rate of decline in leading-edge semiconductor prices to changes in these underlying parameters in the mid-1990s, and explain why measured historical rates of decline over this period seem unlikely to persist. Finally, I explore the nature of the man-made historical and institutional economic processes that made these technical accomplishments possible, and argue that their consequence has been an unappreciated but radical transformation of the industrial framework in which R&D is undertaken within the global semiconductor industry. BACKGROUND In 1965, when Gordon Moore enunciated the first version of this “law,” semiconductor manufacturing accounted for about 0.09 percent of U.S. GDP. (See Table 1.) Thirty-five years later semiconductor manufacturing’s relative size had increased tenfold, and it accounted for almost 1 percent of U.S. GDP. Semiconductors were the single largest manufacturing industry in the United States (more precisely, they were the four-digit industrial code with the largest value added). Furthermore, while in 1965 the United States accounted for the vast bulk of global output, at the dawn of the twenty-first century it only accounted for roughly a third of total world production. The rapid growth of semiconductor manufacturing within the United States must be part of an even steeper rise relative to the size of the global economy. Perhaps more importantly, semiconductors are a critical input to the industries at the heart of information technology: computers and communications. These two industries have had a particularly significant role in U.S. economic and productivity growth over the last decade.2 Together with consumer electron- 2 See Dale Jorgenson, “Information Technology and the U.S. Economy,” American Economic Review, 91(1):1-32, 2001.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium ics, this cluster of user industries also accounted for about seven-eighths of global semiconductor consumption in 2000.3 Rough calculations suggest that improvement in price-performance in semiconductors has been a major (if not the major) source of price-performance improvement in information technology.4 Thus, declines in cost for electronics functionality embedded in semiconductors are the linchpin of improvement in price-performance for computers and communications, which in turn has been a major factor in recent economic performance. To the extent that Moore’s Law is connected to these phenomena, it is of great importance. THE HISTORY OF MOORE’S LAW In 1965, Gordon Moore first noted the developing industry trends that were to become Moore’s Law.5 In a now-famous diagram, Moore plotted a trend line for components per integrated circuit over the previous seven years and projected its continuing for another decade, out to 1975. (See Figure 1.) Moore described this figure as showing the “minimum cost per component”-sized IC (note that Moore uses “component” to refer to what can also be referred to as function or device—i.e., a transistor or elemental unit of electronic functionality). Moore also noted that IC costs were at this point dominated by packaging costs, not the costs of fabricating the silicon semiconductor to be packaged—so that, up so some limit, costs per function/device effectively declined as the inverse of the number of devices per chip. The effective limit to placing more functions/devices on a chip came from sharply decreased manufacturing yields—and sharply higher costs per device—on larger chips past some critical size, defined in terms of devices per chip. The Moore’s Law graph basically plotted Moore’s projection of how this critical “minimum cost” number of devices per chip was likely to change over time. It is important to point out that continually decreasing the size of circuit features by means of technical improvements in the photolithographic processes 3 Author’s calculations based on data from World Semiconductor Trade Statistics, Annual Consumption Survey, 2000. 4 See Jack E. Triplett, “High-Tech Productivity and Hedonic Price Indexes,” in Organisation for Economic Co-operation and Development, Industry Productivity, Paris: OECD, 1996; Kenneth Flamm, “Technological Advance and Costs: Computers vs. Communications,” in Robert C. Crandall and Kenneth Flamm, eds., Changing the Rules: Technological Change, International Competition, and Regulation in Communications, Washington, D.C.: The Brookings Institution, 1989; Ana Aizcorbe, Kenneth Flamm, and Anjum Khurshid, “The Role of Semiconductor Inputs in IT Hardware Price Declines: Computers vs. Communications,” Finance and Economics Discussion Series. Washington, D.C.: Board of Governors of the Federal Reserve System, December 2001. 5 Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, 38(8): 114-117, April 19, 1965.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium FIGURE 1 The Original “Moore’s Law” Plot from Electronics, April 1965. used to pattern silicon wafers with integrated circuits did not play any role in this first version of Moore’s Law. To the contrary, Moore went to great pains to point out that the ICs he was predicting could be manufactured using existing feature sizes and manufacturing technology. Indeed, after Moore notes that his graph implies a single IC with 65,000 components on it by 1975, he states: “I believe that such a large circuit can be built on a single wafer.”6 The integrated circuits projected for the out-years of Figure 1 were visualized as being about the same size as snack-type mini-pizzas. 6 Ibid. Moore notes that the silicon wafers then in use were “usually an inch or more in diameter,” with “ample room for such a structure if the components can be closely packed with no space wasted for interconnection.” He notes that this density “can be achieved by present optical techniques and does not require the more exotic techniques, such as electron beam operations, which are being studied to make even smaller structures.”
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium In 1975, the endpoint of his original prediction, Moore produced a significant revision to his original prediction.7 Most importantly, Moore noted that rather than simply increasing the size of the chip to achieve the greater number of devices (components) per chip, manufacturers had instead used “finer scale microstructures” to engineer a higher density of components per chip. Noting that area per component on a chip was essentially proportional to the minimum dimension per component squared, Moore effectively proposed that (1) components per chip = k * area of chip / area per component where constant k is a residual factor that has been added to reflect “device and circuit cleverness”—i.e., factors above and beyond decreases in the size of the features patterned on a chip and the size of the chip. Equation (1) allows the sources of Moore’s Law to be decomposed into a contribution of component-dimension reduction (1/area per component), a contribution of increased chip size, and a contribution of all other things (“cleverness,” k). The first two can be estimated from technical data and the last calculated as a residual. Using data from the period from 1960 to 1975, Moore calculated that components per chip had increased by about 65,000, that density (1/area per component) had improved by a factor of 32 historically, that chip area had increased by a factor of 20, and that “cleverness” must therefore have improved components per chip by a factor of about 100 over the same period. Moore then went on to argue that, based on current developments, there was no reason to expect that future trends in chip area or density would deviate from the historical pace. “Cleverness,” however, was apparently being exhausted, and Moore proposed that all future contributions from this source could not much exceed another factor of four. Accordingly, Moore revised his law by suggesting that, by the end of decade of the 1970s, increases in components per chip “might approximate a doubling every 2 years, rather than every year.”8 In later years, it became clear that the real world was actually doing better than this 1975 prediction. The de facto barometer for Moore’s Law became the Dynamic Random Access Memory chip (DRAM), first produced in 1970 with 1,024 binary digits (“bits”) of memory on a single chip. New generations of DRAMs typically multiplied the capacity of an older generation by a factor of four every 3 years. Moore’s Law was informally modified and assimilated by the technology community—and the press—as a prediction that components per chip would double every 18 months, the mean of the optimistic Moore of 1965 and the excessively pessimistic Moore of 1975. 7 Gordon E. Moore, “Progress in Digital Integrated Circuits,” Proceedings of the 1975 International Electron Devices Meeting, pp. 11-13, Picataway, NJ: IEEE, 1975. 8 Ibid., p. 13.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium There are, however, no economic predictions embedded in these calculations. Moore’s original 1965 article did project that cost per component would fall to a tenth of its current level by 1970 (which works out to a compound annual decline rate [CADR] of 37 percent). This follows from the assumption that costs per chip were dominated by packaging costs and were assumed to remain constant on a per-chip basis. The 1965 Moore’s Law would predict a tenfold increase in components per chip by 1970 and, therefore, a cost per component of a tenth of 1965 levels by 1970. By 1975, however, chip costs were no longer dominated by packaging of the silicon chip; processes carried out to make the chips themselves in increasingly expensive, high-tech, capital-intensive fabrication plants accounted for the vast bulk of the cost, and packaging for relatively little. THE ECONOMICS OF DECLINING INTEGRATED-CIRCUIT PRICES To understand how continuing technological innovation in semiconductors affects chip costs—and, ultimately, prices—it is helpful to sketch out a stylized description of the principal elements driving the technology and cost structure. To begin, leading-edge semiconductor production is dominated by the costs of fabricating microstructures on silicon wafers: so-called wafer-processing or front-end costs. Assembly and packaging—so-called back-end costs—are relatively small for advanced, leading-edge products, and they will be ignored in the analysis of high-level trends that follows.9 A substantial number of the chips coming out of a wafer-fabrication facility have manufacturing defects and are scrapped. What is left—“yielded” good product—is what gets sold. Typically, the fraction of the chips that is good, as a share of the chips starting down the line on silicon wafers, increases with experience in manufacturing the chip. This so-called learning curve generates increased yields over time and results in the sharp increase over time of yielded good output coming off a fully utilized fabrication line. Again, because we are mainly concerned with long-term trends, we will ignore the impact of learning on yields and assume some fixed, idealized yield of good chips as a fraction of all chips on silicon of some given generation of technology starting down the fabrication line. Integrated-circuit fabrication requires the coordination of many different pieces of technology that have to work together in a very complex manufacturing 9 For a more comprehensive discussion of IC manufacturing and cost structures, see Kenneth Flamm, “Measurement of DRAM Prices: Technology and Market Structure,” in Murray F. Foss, Marilyn E. Manser, and Allan H. Young, eds., Price Measurements and Their Uses, Chicago: University of Chicago Press, 1993; Kenneth Flamm, Mismanaged Trade? Strategic Policy and the Semiconductor Industry, Washington, D.C.: The Brookings Institution, 1996, chapter 6.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium process. In many respects, the pacing technology for the entire process has been photolithography, the critical set of tools used to define and fabricate features on a chip. (Other key techniques combined with lithography to produce microstructures on a silicon wafer include: various methods for deposition and etching of a variety of materials on a silicon substrate; annealing; polishing surfaces; and the creation and maintenance of ultra-clean, contaminant-free spaces in which these advanced processes are carried out.) In recent decades, a new “technology node”—consisting of a new generation of lithographic equipment and the related equipment and materials required for its application—has typically been introduced every three years. The fact that this cycle is the same as that observed historically for the arrival of a new generation of DRAM is no coincidence. DRAMs historically were the highest-volume leading-edge product sold in the marketplace, and new manufacturing technology was typically first implemented in leading-edge memory chip production facilities. Finally I note that, historically, every generation of lithographic equipment has typically shrunk minimum feature size by about 30 percent relative to the minimum feature size produced by the prior generation of equipment. As a result, area per chip feature, or area per component, has declined by 50 percent with each new technology node. We can now derive a relationship between Moore’s Law and cost trends for integrated circuits. The key identity is where each of the variables on the right-hand side has a well defined economic or technical meaning. Moore’s Law, strictly speaking, is about the denominator only—a prediction that components per chip would quadruple every three years. (This is the recent folklore incarnation of Moore’s Law; the published 1965 version would have quadrupled components per chip every 2 years, and the published 1975 version every 4 years.) The chip containing the increasing numbers of components could conceivably be the size of a full-sized pizza—and costs per component might well rise rather than fall. However, the introduction of 30 percent smaller feature dimensions every three years would result in 50 percent smaller areas per component. With four times the components on a next-generation chip, then, the silicon area per chip would only double, rather than quadruple. Finally, average processing cost per total wafer area processed has increased only slightly in recent years; wafer-processing costs have increased greatly, but
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium so have wafer sizes and areas.10 If we also factor in a trend to steadily rising yields as successive generations of products reach volume production, it seems conservative to propose that wafer-fabrication costs per area of good silicon have remained roughly constant.11 If we now substitute in these stylized trends—a wafer-processing cost per area of silicon that is constant, silicon area per chip that doubles as components per chip quadruple, and a new technology node that is introduced every three years—we can do some simple math using Equation (2). The calculation suggests that every three years, the cost of producing a component in silicon will fall by 50 percent, for a CADR of 21 percent annually. To summarize, if we further assume a new technology node shrinking area per component by 50 percent every three years, constant wafer-processing costs per area of good silicon, and prices roughly tracking unit costs in the long run, an economist’s corollary to Moore’s Law would be a 21 percent annual decline in price-performance for leading-edge semiconductors. THE INGENUITY (DRAM) COROLLARY If we actually survey economists’ attempts to measure price-performance in semiconductors, however, we discover something remarkable. Our impressive forecasts of large improvements in price-performance for microelectronic components are far too stingy when compared with the actual historical record. Table 2 shows some recent estimates of quality-adjusted price indexes for what are probably the two most important types of leading-edge ICs, DRAMs and microprocessors. Over the 22 years from 1974 to 1995, both DRAMs and microprocessors fell at an annual rate of roughly 30 percent.12 10 Over the 1983-1998 period, one estimate is that overall wafer-processing cost per square centimeter of silicon increased at a compound annual growth rate of 5.5 percent. See Carl Cunningham, Denis Fandel, Paul Landler, and Robert Wright, “Silicon Productivity Trends,” International SEMATECH Technology Transfer #00013875A-ENG, February 29, 2000, p. 5. Note that this estimate is per total silicon area processed, not cost per good yielded area. Since good yielded area appears to have increased over time as a fraction of total wafer area processed, with improved processing yields, it seems safe to assume that wafer processing cost per good yielded silicon area was roughly constant over time. 11 For solid evidence that DRAM yields have increased steadily over time, for successive generations of DRAMs, see Charles H. Stapper and Raymond J. Rosner, “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, 8(2), 1995, p. 100; Rainier Cholewa, “16M DRAM Manufacturing Cooperation IBM/ SIEMENS in Corbeil Essonnes in France,” Proceedings of the 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Piscataway, NJ: IEEE, 1996, p. 222. 12 See Kenneth Flamm, More For Less: The Economic Impact of Semiconductors, San Jose, CA: Semiconductor Industry Association, 1997, Appendix 2.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium TABLE 2 Decline Rates in Price-Performance Percent/Year Microprocessors 1975-1985 –37.5 Hedonic Index 1985-1994 –26.7 DRAM Memory 1975-1985 –40.4 Fisher Matched Model 1985-1994 –19.9 DRAMs, Fisher Matched Model, Quarterly Data 91:2-95:4 –11.9 95:4-98:4 –64.0 Intel Microprocessors, Fisher Matched Model, Quarterly Data 93:1-95:4 –47.0 95:4-99:4 –61.6 SOURCES: Flamm (1997); Aizcorbe, Corrado, and Doms (2000). Remarkably, then, both DRAMs and microprocessors were falling at a rate roughly 50 percent greater than that we just calculated in our economic corollary to Moore’s Law! In fact, for the first half of this period, these rates are almost identical to those projected by Moore I for the late 1960s and early 1970s. Moreover, this was over the period 1975-1985, when Moore II suggested a significant slowing in the pace of technical innovation in semiconductors. The much-anticipated slowdown seems instead to have occurred a decade later, over 1985-1995. This was an exceptional period in the history of the industry, rife with international trade frictions, government policy activism, and—near its end—an unprecedented burst in world demand for chip-guzzling personal computers. How did this first pass at a simple economic corollary to Moore’s Law go wrong over these decades? The most obvious candidate inaccuracy seems to be its assumption that chip size would double from one technology node to the next. In fact, chip size seems to have increased by substantially less than a factor of two from one technology node to the next. In the case of the DRAM, over this period average chip size seems to have increased by a factor of about 1.4 from one node to the next.13 13 One calculates a factor of 1.37 based on chip area for first versions of six generations of DRAMs. The increase in size is calculated from the data shown in Figure 6.2 in Betty Prince, Semiconductor Memories: A Handbook of Design, Manufacture and Application, 2nd Edition, Chichester, UK: John Wiley and Sons, 1991, p. 209. A similar estimate is implicit in Cunningham, Fandel, Landler, and Wright, op.cit., p. 11, who estimate that area/bit has fallen at a rate of 29 percent annually over a long period. That works out to an increase in chip size of 41 percent with every three-year quadrupling in bits per DRAM.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium DRAM chip sizes increased by less than what is implied by shrinkage of features owing exclusively to improved lithographic equipment because of the old standby of Moore’s 1975 paper: cleverness. In fact, there was considerable further ingenuity applied in the design of DRAMs. In particular, after roughly a decade in which further generations of DRAMs in essence scaled down the basic DRAM design of the mid-1970s to smaller dimensions, a period of vigorous innovation began in the late 1980s during which three-dimensional memory cells were developed.14 In addition to 3-D features in memory cells, use of additional interconnect levels allowed tighter packing of components on a chip, and other types of products moved closer to the leading edge in their use of advanced manufacturing process technology.15 The net result was an average chip size that increased significantly less than that associated with reduced feature size due to introduction of a new technology node alone. In the case of DRAMs, the increase in chip size was about 30 percent less than that predicted on the basis of lithography improvement alone.16 We can incorporate this ingenuity factor as an additional variable, K, in Equation (2) by noting that “silicon area/chip” in Equation (2), rather than doubling every three years (as it would were area/chip altered by the lithography innovation associated with a new technology node alone), increases by 2K where K (<1) denotes an additional reduction factor in chip size due to other design and process innovation. With the historical pattern of design innovation in DRAMs we have just seen, K equals approximately 0.7. If we then redo the math based on Equation (2) with a new technology node every three years, constant wafer-processing cost, and chip size increasing by multiple 2K (=1.4), we produce an annual decline rate of 30 percent. That this is the historical rate of decline in DRAM price (quality-adjusted) over the 1974-1995 period is not completely surprising, since we have in effect used the DRAM to calibrate our estimated impact of design ingenuity, parameter K. What is more reassuring is that the methodology used for calculating quality-adjusted prices over this period makes no use of the technical parameters and predictions embedded in Equation (2) yet gives us completely consistent and congruent descriptions of trends in costs and prices.17 14 See Prince, op. cit., pp. 209-210, for an overview. 15 Cunningham, Fandel, Landler, and Wright, op. cit., p. 4. 16 I.e., chip size increased by about 1.4 rather than 2, for about a 30 percent reduction in chip size relative to that predicted by lithography alone. 17 The methodology used for producing the price indexes cited in Flamm, More for Less, takes weighted averages of “matched model” DRAM chip market prices from one period to the next, with the weights calculated from market revenue shares for each model according to the so-called Fisher ideal index number formula. It does not use any information on price per bit or any other direct calculation of price per electronic element or function. Interestingly, though not a perfect correlation, the Fisher ideal price index and a simple calculation of average price per aggregate bit shipped for all generations of chips produced at any moment are a close match over time. See Flamm, Mismanaged Trade, pp. 10 and 238-239.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium What remains intriguing is that the decline in DRAM prices was substantially greater than this (a CADR of 37 percent) over the subperiod 1975-1985. One possible explanation is that Equation (2) captures some notion of long-run average cost, and that a lot of other factors—fluctuations in demand, entry by new competitors, exit by others, the impacts of trade and industrial policy—have shorter-term impacts on market price quite separate from long-term cost fundamentals. This is certainly true, but an additional explanation is that processing cost per silicon area was not really constant over this early, data-deficient period—that it was instead declining in a way not captured in the above calculations. In the late 1970s, Japan’s government, in close cooperation with national semiconductor producers, launched a series of cooperatively funded R&D projects: the so-called VLSI Projects, which were perceived in the United States (and in Japan, for that matter) as having greatly advanced the technological and manufacturing competence of Japanese semiconductor producers.18 A 1987 Defense Science Board report pointing to deterioration in the relative position of American semiconductor manufacturers as a possible national security issue played an important role in a U.S.-government decision to have the Defense Department pay half of the cost of a joint industry consortium, dubbed SEMATECH (for semiconductor manufacturing technology) and budgeted at $200 million annually. Thus, it can be argued that the early 1980s were a period in which Japanese equipment manufacturers and IC producers were significantly improving semiconductor manufacturing technology, building in part on the technical successes of the VLSI Projects. Indeed, U.S. semiconductor manufacturers in later years acknowledged that they were lagging Japanese producers in manufacturing technology over this period, and that the formation of SEMATECH was part of their recognition of this problem.19 It is not unreasonable to suggest that the Japanese entry into the global semiconductor market in the late 1970s and early 1980s was at least in part based on improvements in semiconductor manufacturing techniques which may well have been associated with significant declines in wafer-processing costs—in sharp contrast with the apparent stability of these costs in later decades that has been documented. 18 See Flamm, Mismanaged Trade, chapter 2; J. Sigurdson, Industry and State Partnership in Japan: The Very Large Scale Integrated Circuits (VLSI) Project, Lund, Sweden: Research Policy Institute, 1986; for detailed discussions of the Japanese VLSI projects and their impact. A “revisionist” assessment can be found in M. Fransman, The Market and Beyond: Cooperation and Competition in Information Technology Development in the Japanese System, Cambridge, UK: Cambridge University Press, 1992. 19 See Flamm, Mismanaged Trade, pp. 144-146, on this point.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium TINKERING WITH MOORE’S LAW: THE TECHNOLOGY ROADMAP PROCESS While the objective of improving American semiconductor manufacturing technology was fairly clear, the specific means by which SEMATECH was to meet it were the subject of considerable debate, and SEMATECH’s focus zigged and zagged in its first few years of existence. It was restricted to American companies; Japanese producer NEC, which had a U.S. production plant, was turned away when it sought to join in 1988.20 SEMATECH underwent significant changes in structure and research direction in the early 1990s. Even in the early years, there had been a growing emphasis on projects designed to improve the equipment and materials used by U.S. semiconductor makers but purchased from upstream equipment and materials producers. In 1992, after a new CEO had been brought on board and an internal reorganization undertaken, a new long-range plan (SEMATECH II) was adopted.21 One new emphasis was on a significant reduction in the elapsed time between introductions of new technologies. Coinciding with this new emphasis on more rapid introduction of new technologies at SEMATECH was the institutionalization and acceptance within the U.S. semiconductor industry of a so-called roadmap process: a systematic attempt by all major players both in the U.S. IC industry and among its materials and equipment suppliers to jointly work out details of a complex array of likely new technologies required for manufacturing next-generation chips, coordinate the required timing for their introduction, and intensify R&D efforts on the pieces of technology that were likely to be “showstoppers” and required further work if the overall schedule was to succeed. The first such “national technology roadmap” was published in 1992, and the next one, issued in 1994, still had new technology nodes being introduced at the historical three-year intervals.22 But the so-called 250-nanometer technology node was introduced a year earlier than called for in the 1994 Roadmap, and the 1997 National Technology Roadmap called for the next technology node (at 180 20 Good resources on the history of SEMATECH are SEMATECH’s own web pages (at <www.SEMATECH.org>), and the corporate chronology contained within; W. J. Spencer and P. Grindley, “SEMATECH After Five Years: High Technology Consortia and U.S. Competitiveness,” California Management Review, 35, 1993; P. Grindley, D. C. Mowery, and B. Silverman, “SEMATECH and Collaborative Research: Lessons in the Design of a High-Technology Consortia,” Journal of Policy Analysis and Management, 13, 1994; L. D. Browning and J. C. Shetler, SEMATECH, Saving the U.S. Semiconductor Industry, College Station, TX: Texas A&M Press, 2000; John Brendan Horrigan, “Cooperation Among Competitors in Research Consortia,” unpublished doctoral dissertation, University of Texas at Austin, December 1996. 21 See Browning and Shetler, op. cit., chapter 8. 22 See Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1994, San Jose, CA: Semiconductor Industry Association, 1994.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium nm) to follow after another two-year interval rather than reverting to the three-year pattern.23 It is far from clear that this acceleration of technological improvement in the semiconductor industry was solely the result of decisions taken within the membership of the U.S. SEMATECH consortium and the broader industry, government, and academic coalition participating in the U.S. national technology roadmap process. Korean producers had become major players on the world semiconductor scene, and Taiwanese manufacturers were rapidly becoming a significant force. Accelerating competitive pressures were certainly being felt by U.S. chip producers, and intensified efforts to more rapidly deploy new technology were a logical economic response. But the identification of R&D needs and explicit coordination of R&D efforts through an industry-wide program was a novel and important development.24 Other institutional changes coincided with this industry-wide shift toward a two-year technology node pace. In 1995 a decision was made by SEMATECH to partner with foreign companies in a project aimed at accelerating the development of technology designed for use with 300-mm (12-in.) silicon wafers. In fiscal 1996 U.S. government funding for SEMATECH ended by mutual agreement. In 1998 a separate organization, International SEMATECH, was formed as the umbrella for an increasing number of projects in which non-U.S. chip producers were involved, and in 1999 the original SEMATECH restructured itself into International SEMATECH. Interestingly, International SEMATECH in 2002 has 13 corporate members (eight American, five foreign), the same number as the parent SEMATECH had when founded. The share of world semiconductor sales accounted for by the consortium’s membership is now substantially greater than was the case in 1987.25 SEMATECH was also certainly perceived as a major force in Japan, where the SEMATECH model greatly influenced the formation of a new generation of semiconductor industry R&D consortia in the mid-1990s.26 The Japanese semiconductor industry’s R&D consortium, known as SELETE, was joined by Korean producer Samsung, and there are in effect two rival international R&D orga- 23 See Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, Technology Needs, 1997 Edition, San Jose, CA: Semiconductor Industry Association, 1997. 24 The existence of the National Cooperative Research Act of 1984, which granted partial antitrust exemption to registered U.S. R&D consortia—like SEMATECH, the operational home for the U.S. roadmap—undoubtedly played an important role in making this roadmap coordination process feasible for the industry. 25 It is claimed that prior to its internationalization, the SEMATECH membership never accounted for less than 75 percent of U.S. semiconductor industry sales. Shetler and Brown, op. cit., p. 197. 26 See Kenneth Flamm, “Japan’s New Semiconductor Technology Programs,” Asia Technology Information Program Report No. ATIP 96.091, Tokyo, November 1996.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium nizations within the global semiconductor industry today: SELETE, headquartered in Japan, and International SEMATECH, with headquarters in the United States. The 1997 roadmap was the last “national” technology roadmap. Later roadmaps are “International Technology Roadmaps” sponsored and coordinated through the two global R&D consortia and through national semiconductor industry associations headquartered in the United States, Europe, Japan, Korea, and Taiwan.27 A two-year cycle for the introduction of new technology nodes remains a feature of recent roadmaps, though they also call for a reversion to the slower-paced three-year cycle after 2005.28 An earlier call for reversion to a longer cycle (in the 1999 international roadmap), incidentally, was ignored when the 130-nm technology node was introduced in 2001, just two years after the 180-nm node had come online. THE IMPACT OF FASTER INNOVATION ON IC COST Let us now consider the economic impact of the move from a three-year cycle to a two-year cycle in the introduction of a new technology node. If we assume that Moore’s Law obliges with a similar acceleration (i.e., a quadrupling of components per chip in two years—the original Moore 1965 pace) on the same schedule as a new technology node, as was historically the case in DRAMs, then the default calculation (no further application of ingenuity in reducing chip size, K=1) of declines in cost per component based on Equation (2) produces a CADR of 29 percent. With the historical dose of ingenuity a la DRAM continuing (i.e., K=0.7, chip size shrinking an additional 30 percent above and beyond the size associated with the lithography introduced over the faster two-year cycle), the CADR improves to 41 percent annually. If we were to heroically assume that chip size were to remain constant, reflecting even greater applications of ingenuity—which some in the industry have publicly called for as a new target in R&D roadmaps (i.e., K=0.5)—then a decline in cost per component as high as 50 percent annually would result. These are impressively large numbers. Incredibly, even with the most generous assumptions about technological acceleration and further ingenuity in design and manufacturing, they fall short of the actual historical record for quality-adjusted DRAM and microprocessor prices in the late 1990s, which fell at rates exceeding 60 percent per year! (See Table 2.) 27 They may be accessed through a link found at the International SEMATECH web site, at <www.sematech.org>. 28 According to the 2000 International Technology Roadmap.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium FIGURE 2 Quality-adjusted price change in DRAMS and microprocessors. SOURCE: Author’s calculations based on Aizcorbe, Corrado, and Doms (2000). CAUSES AND CONSEQUENCES OF DECLINING COSTS This acceleration in the decline of semiconductor prices has been noted by economists and credited with playing a significant role in the macroeconomic productivity growth acceleration of the late 1990s, as well as an important role in more rapidly declining prices for the underlying computer and communications capabilities which fueled the technology contribution to resurgent productivity.29 It is also tempting to speculate that this decline in the cost of computing and communications capabilities played a significant role in the boom in Internet-related activities that occurred over this same period. Indeed, the graphical evidence of price movements over the decade of the 1990s seems to support the notion of a “point of inflection” in the pace of technological advance in leading-edge semiconductors in the mid-1990s. Figure 2 shows one set of measurements of quality-adjusted price change in DRAMs and microprocessors over this period. 29 Jorgenson, op. cit.; Aizcorbe, Flamm, and Khurshid, op. cit.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium But this analysis suggests that while some of the more rapid technological advance and more rapidly declining prices in semiconductors are attributable to identifiable long-term changes in the pace of technical innovation in semiconductors, a substantial portion of the more rapid decline in semiconductor prices in the late 1990s must be due to more transitory changes. Likely candidates include cyclical fluctuations in product demand, intensified competition (which may well end in some consolidation within this global industry as the least successful exit the industry), a shift of manufacturing processes for some products closer to the leading edge in technology, and a shortening of product lives accompanying more frequent introductions of new versions of certain products. All of these would have some transitory impact in accelerating declines in price, but they will likely dissipate as the industry approaches a new “steady state.” In short, if one accepts this analysis of the technical and economic fundamentals determining cost on the “supply side,” the pace of price declines of the late 1990s cannot be sustained. Leading-edge semiconductors may well drop in price at much faster rates than in the past as the result of faster introduction of new technology nodes over the long term, but the increase will be from 30 percent annually to a number in the 40 percent-plus range, not in a range exceeding 60 percent annual declines. One would also expect productivity improvement flowing directly and indirectly from the sharp price declines for information technology of the late 1990s to fall to more moderate—but sustainable—levels in future years. THE DYNAMICS OF MOORE’S LAW Finally, it is worth noting that Moore’s Law can be interpreted as an interesting case of an informal institutional framework for analyzing technical change that gradually evolved into a more formally structured process for organizing technical change in a major global industry. There was nothing inevitable about Moore’s Law—no underlying technical or physics-based reason for the phenomenon. (In fact, as already noted, the original 1965 Moore’s Law did not rely on any significant technical change!) Instead, Moore’s Law through the 1980s can perhaps be interpreted as a self-reinforcing expectations mechanism. Companies believed something approximating Moore’s prediction, and as it continued to more or less hold true, companies made their technical plans around sticking to a Moore’s Law timetable. This was probably not because that schedule would necessarily have maximized their profit had everyone else not innovated on the same timetable, but because they believed that all their competitors would be introducing new products and technology on the Moore’s Law schedule and that, therefore, they too had to stick to the plan in order to stay competitive. This certainly seems to have been the case in DRAMs, the pacing product for new semiconductor manufacturing technology, where a three-year next generation product introduction schedule became an accepted characteristic of the market.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium Then, in the 1990s, as the U.S. SEMATECH consortium finally defined it-self, a new and more formal coordination mechanism for R&D came into play. Rather than simply accepting a historical norm, a decision was made to alter the norm by trying to explicitly coordinate the now-complex array of decentralized pieces of technology that had to be simultaneously improved in order to bring a new generation of manufacturing systems online. It may be impossible to determine the extent to which the coordination process played a role, or the extent to which the simple act of a major group of IC producers announcing new and very specific technology targets created a credible reason for the various suppliers of technology to believe that the technology cycle really was about to accelerate, and therefore caused it to accelerate. What is clear is that the industry roadmap—the ultimate descendent of Moore’s Law—has now become an organizing and coordinating framework for private and public R&D in what is the largest, most important, and most globalized manufacturing industry in the world. The executive agents for this organizing framework were originally national in character. The U.S.’s SEMATECH consortium and Semiconductor Industry Association originally treated the whole process as a national endeavor, designed to give national producers a leg up over the global competition. But reality—that U.S. companies were not necessarily the leaders in all of the many bits of technology that had to be coordinated for the next-generation manufacturing line to work, and that both semiconductor producers and their suppliers were thoroughly international in all aspects of their business operations, from R&D, to manufacturing, to sales—led the U.S. industry to reach out to global partners. First SEMATECH, then the roadmap, added the prefix “International” to their name. Today, the roadmap process is thoroughly global in character. Interestingly, there are two competing multinational R&D consortia—International SEMATECH, with no Japanese members, and SELETE, with just one, very large non-Japanese member—that manage to balance nationalist dynamics and international coalitions within a single, overarching international R&D roadmap coordination process. Economists are largely accustomed to thinking of the speed of technological change as something that is exogenous, dropping in gracefully from outside their models. Ultimately, one moral of this story is that the pace of technological change in the semiconductor industry may have an endogenous component as important as its exogenous scientific foundations. Particularly where many complex items of technology secured from a broad variety of sources must be coordinated in a fairly precise manner in order to create economically viable new technological alternatives, vague and diffuse factors like expectations and even political coalitions may play an important role. CONCLUSIONS This paper has constructed a simple framework for explaining how technological trends in the semiconductor industry are ultimately reflected in the dy-
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium namics of costs and—in the long run, in a competitive industry—leading edge chip prices. The framework does a reasonable job of tracking real-world, quality-adjusted price trends for leading-edge products over the 1975-1995 period. Moore’s Law governs one of the three key technical and economic variables that drive the calculation. Moreover, the same framework suggests that an acceleration in the introduction of new technology nodes in the late 1990s had a significant and predictable impact in further increasing the rate of decline in leading edge chip prices that took place at that time. These calculations, however, indicate that the actual fall in these prices over this period substantially exceeded the decline attributable to sustainable, long-term cost trends, suggesting that the extraordinary price declines of the late 1990s—in excess of 60 percent for memory chips and microprocessors—were transitory in nature. Even with optimistic assumptions about further innovation, I conclude that price declines must moderate significantly from these stratospheric rates over the long haul. To the extent that macroeconomic productivity growth and robust sales of information technology over this period were based on these component cost foundations, they too must fall back to more moderate rates in the future. Finally, I noted that Moore’s Law was more of an expectation than a physical law, and I pointed out that an informal benchmark for coordinating R&D has since been replaced with a formal, globalized technology roadmap process. Here we must also end on a note of caution. We now have—with little fanfare or publicity—a situation in which what has become the most important manufacturing industry in the world, an industry made up of fierce competitors from all over the globe, calls a truce and jointly negotiates a set of global targets for private and public R&D efforts. What the roadmap gives, the roadmap can also take away. Recent roadmaps, while continuing to call for two-year technology nodes in the near term, have perhaps wistfully or nostalgically also called for a return to an older, slower pace of technological change toward the end of this decade. Recent roadmaps have also suggested slowing down the pace of new-product introductions in DRAMs in the future, calling for a quadrupling of memory bits on a chip every four years instead of the historical three-year interval. While these choices may be dictated by technical issues, the roadmaps provide a framework in which economic implications can be discussed when technical choices are set cooperatively. The current roadmap process seems to be open and transparent. But because the roadmap framework for guiding technological change in this thoroughly global industry is international, the role of national governments in drawing the fine line between acceptable cooperation and unacceptable collusion may at some point need to be revisited. Whether or not this becomes an issue, we cannot ignore the emergence of a pioneering new model for international R&D cooperation within the largest global high-tech industry.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium REFERENCES Aizcorbe, Ana, Kenneth Flamm, and Anjum Khurshid. 2001. “The Role of Semiconductor Inputs in IT Hardware Price Declines: Computers vs. Communications” Finance and Economics Discussion Series. Washington, D.C.: Board of Governors of the Federal Reserve System. December. Browning, L. D., and J. C. Shetler. 2000. SEMATECH, Saving the U.S. Semiconductor Industry. College Station, TX: Texas A&M Press. Cholewa, Rainier. 1996. “16M DRAM Manufacturing Cooperation IBM/SIEMENS in Corbeil Essonnes in France” Proceedings of the 1996 IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Piscataway, NJ: IEEE. p. 222. Cunningham, Carl, Denis Fandel, Paul Landler, and Robert Wright. 2000. “Silicon Productivity Trends.” International SEMATECH Technology Transfer #00013875A-ENG. 29 February. Flamm, Kenneth. 1989. “Technological Advance and Costs: Computers vs. Communications” in Robert C. Crandall and Kenneth Flamm, eds.. Changing the Rules: Technological Change, International Competition, and Regulation in Communications. Washington, D.C.: The Brookings Institution. Flamm, Kenneth. 1993. “Measurement of DRAM Prices: Technology and Market Structure,” in Murray F. Foss, Marilyn E. Manser, and Allan H. Young, eds. Price Measurements and Their Uses. Chicago: University of Chicago Press. 1993. Flamm, Kenneth. 1996a. “Japan’s New Semiconductor Technology Programs.” Asia Technology Information Program Report No. ATIP 96.091. Tokyo. November. Flamm, Kenneth. 1996b. Mismanaged Trade? Strategic Policy and the Semiconductor Industry. Washington, D.C.: The Brookings Institution. Flamm, Kenneth. 1997. More For Less: The Economic Impact of Semiconductors. San Jose, CA: Semiconductor Industry Association. Fransman, M. 1992. The Market and Beyond: Cooperation and Competition in Information Technology Development in the Japanese System. Cambridge, UK: Cambridge University Press. Grindley, P., D. C. Mowery, and B. Silverman. 1994. “SEMATECH and Collaborative Research: Lessons in the Design of a High-Technology Consortia” Journal of Policy Analysis and Management. 13. Horrigan, John Brendan. 1996. “Cooperation Among Competitors in Research Consortia.” Unpublished doctoral dissertation. University of Texas at Austin. December. Jorgenson, Dale. 2001. “Information Technology and the U.S. Economy” American Economic Review. 91(1): 1-32. Moore, Gordon E. 1965. “Cramming More Components onto Integrated Circuits” Electronics. 38(8): 114-117. 19 April. Moore, Gordon E. 1975. “Progress in Digital Integrated Circuits” Proceedings of the 1975 International Electron Devices Meeting. pp. 11-13. Piscataway, NJ: IEEE. Prince, Betty. 1991. Semiconductor Memories: A Handbook of Design, Manufacture and Application, 2nd Edition. Chichester, UK: John Wiley and Sons. Semiconductor Industry Association, 1994. The National Technology Roadmap for Semiconductors, 1994. San Jose, CA: Semiconductor Industry Association. Semiconductor Industry Association. 1997. The National Technology Roadmap for Semiconductors, Technology Needs, 1997 Edition. San Jose, CA: Semiconductor Industry Association. Sigurdson, J. 1986. Industry and State Partnership in Japan: The Very Large Scale Integrated Circuits (VLSI) Project. Lund, Sweden: Research Policy Institute. Spencer, W. J., and P. Grindley. 1993. “SEMATECH After Five Years: High Technology Consortia and U.S. Competitiveness” California Management Review. 35. Stapper, Charles H. and Raymond J. Rosner. 1995. “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation” IEEE Transactions on Semiconductor Manufacturing. 8(2):100.
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Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions - Report of a Symposium Triplett, Jack E. 1996. “High-Tech Productivity and Hedonic Price Indexes” in Organisation for Economic Co-operation and Development. Industry Productivity. Paris: Organisation for Economic Co-operation and Development. World Semiconductor Trade Statistics. 2000. Annual Consumption Survey.
Representative terms from entire chapter: