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The Quest for the Next Information-Processing Technology

JEFFREY J. WELSER

IBM Almaden Research Center

San Jose, California


In recent semiconductor technology generations, exponentially increasing power density has started to limit the historical benefits of scaling. Thus researchers are looking for entirely new device approaches and methods of computation in emerging nanoscale technologies. The Nanoelectronics Research Initiative (NRI) is taking on the grand challenge of finding a “new switch” that can continue the exponential increase in information-processing capability, which has benefited not only the semiconductor industry, but nearly every aspect of our electronics and information technology-driven modern economy.

INTRODUCTION

For more than three decades, the semiconductor industry has been driven by its ability to scale the size of the complementary metal oxide semiconductor (CMOS) field-effect transistor (FET), the key building block in modern integrated circuit (IC) chips. This scaling has enabled the industry to pack twice as many FETs onto a chip every 18–24 months, in what has come to be known as “Moore’s law” (Moore, 1965). The result has been an exponential increase in the



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The Quest for the Next Information-Processing Technology Jeffrey J. WelSer IBM Almaden Research Center San Jose, California In recent semiconductor technology generations, exponentially increasing power density has started to limit the historical benefits of scaling. Thus research- ers are looking for entirely new device approaches and methods of computation in emerging nanoscale technologies. The Nanoelectronics Research Initiative (NRI) is taking on the grand challenge of finding a “new switch” that can continue the exponential increase in information-processing capability, which has benefited not only the semiconductor industry, but nearly every aspect of our electronics and information technology-driven modern economy. INTRODUCTION For more than three decades, the semiconductor industry has been driven by its ability to scale the size of the complementary metal oxide semiconductor (CMOS) field-effect transistor (FET), the key building block in modern inte- grated circuit (IC) chips. This scaling has enabled the industry to pack twice as many FETs onto a chip every 18–24 months, in what has come to be known as “Moore’s law” (Moore, 1965). The result has been an exponential increase in the 4

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4 FRONTIERS OF ENGINEERING information-processing capability per unit area on the chip—or more importantly, per dollar. Recently, exponentially increasing power density, due to both FET leakage currents and switching energy, has limited the continuation of scaling. Recogniz- ing that the fundamental physics of FET operation, rather than fabrication capa- bility, are likely to impose an ultimate limit on continued scaling in the next 10 to 15 years, researchers are now on a quest for new devices that can continue the trends in information-processing performance. To take on this grand challenge, the NRI (nri.src.org) was formed in 2004 as a consortium of Semiconductor Industry Association (SIA) (www.sia-online. org) companies to manage a university-based research program as part of the Semiconductor Research Corporation (SRC) (www.src.org). Founded by six U.S. semiconductor companies (AMD, Freescale, IBM, Intel, Micron, and TI), NRI partners with the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), and state governments to sponsor research currently at 35 U.S. universities in 20 states. THE NANOELECTRONICS RESEARCH INITIATIvE The overall goal of NRI is to demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 time frame. To enable the semiconductor industry to continue the historical cost and performance trends for information technology, these new devices must have a significant advantage over ultimate FETs in power, performance, density, and/or cost. To meet these goals, NRI has focused primarily on research on devices that use new computa- tional-state variables beyond electronic charge. In addition, NRI is investigating new interconnect technologies and novel circuits and architectures, includ- ing nonequilibrium systems, for exploiting these devices, as well as improved nanoscale thermal management and novel materials and fabrication methods for structures and circuits. Finally, it is hoped that these technologies will be capable of integrating with CMOS so that their potentially complementary functionality can be exploited in heterogeneous systems and can enable a smooth transition to a new scaling path. PHYSICS OF A LOGIC SWITCH As outlined in the 1970s (Dennard et al., 1974), if one shrinks the critical dimensions of an FET by a factor kappa, while simultaneously increasing the doping levels and decreasing the applied voltages by the same factor, the scaled transistor switches faster but consumes half the power and takes up half the area. This means that twice as many transistors can fit in the same area without decreas- ing power density—the primary reason scaling works without melting the chip.

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4 QUEST FOR THE NEXT INFORMATION-PROCESSING TECHNOLOGY Leakage currents, however, increase as dimensions shrink; leakage occurs along the transistor channel when the switch is turned off and across the gate insulator, which has become so thin (<1.5 nm, or just a few atomic layers) that quantum tunneling dominates. The leakage power is now becoming equivalent to the active switching power of the transistor. The 2001 International Technology Roadmap for Semiconductors (ITRS) Emerging Research Device Technical Working Group conducted a highly sim- plified analysis of a generic electronic switch at thermal equilibrium (zhirnov et al., 2003). The switch was modeled as a potential barrier separating two quantum wells, corresponding to the simplest version of an FET channel between source and drain contacts. The analysis showed that the channel could conceivably be scaled down to ~1.5 nm and that the transistor could have a minimum switch- ing speed of ~40 fs—significantly smaller and faster than today’s FETs of about 30 nm in channel length with ~1 ps switching time. However, to avoid leakage over the barrier at room temperature, the voltage could not be scaled as rapidly as the physical dimensions, and the resulting power density for these switches at maximum packing density would be on the order of 1 MW/cm2—orders of mag- nitude higher than the practical air-cooling limit of ~100 W/cm2. Because the theory does not take into account the materials or structures used, it is applicable to any switch that moves charge dissipatively across a potential barrier. This leads to two implications: (1) Simply shrinking an FET to the far nanoscale will not necessarily continue to give the historical benefit of scaling, because the increasing power density will require trading off switching speed for packing density. (2) The existing Si FET road map is likely to reach the minimum practical dimensions in the next 10 to 15 years (ITRS, 2007); although new FET materials or geometries can improve performance, they will not alter the ultimate scaling limits. NANOELECTRONICS RESEARCH AREAS We need a new “switch” for information processing to significantly extend the scaling path. To define research directions, groups from industry, government, and academia have participated in workshops sponsored by SRC, NSF, and SIA (Cavin and zhirnov, 2004; Cavin et al., 2005, 2006). Thirteen research vectors were defined, and the top five comprise the NRI research program. New Devices: Alternative Computational State vectors An FET device moves electrons dissipatively to charge (discharge) capacitors to represent a binary “1” (“0”). NRI research focuses on finding alternative ways to represent these states or information in general. Any physical property that can be placed into two or more distinguishable states could potentially be used to rep- resent information. One example is to use the spin of an electron, with spin “up”

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4 FRONTIERS OF ENGINEERING representing “1” and spin “down” representing “0.” Spin is already used success- fully in memory and storage devices, so the challenge is injecting, manipulating, and reading out the spin state of an electron or collection of electrons to build logic gates and circuits. Many different devices are being considered under the broad heading of “spintronics” (zutic et al., 2004). Many other materials offer different potential states that could be exploited for logic, including ferroelectric, antiferroelectric, ferromagnetic, antiferromag- netic, ferrotoroidic, ferroelastic, and ferrimagnetic materials (Eerenstein et al., 2006). Even the physical movement of atoms could be considered as a new state variable. Even though atoms are more massive than electrons, it would only be necessary to move them on the order of angstroms to cause large changes in a material (e.g., changing the dipole in a ferroelectric or changing barrier heights at an interface), so that the speed and energy could still be reasonable. And for nanoscale devices, more massive particles are less likely to lose their state by tunneling (zhirnov and Cavin, 2008). Much of the work on new state variables relies on the development of new materials. Dilute magnetic semiconductors have the potential to introduce spin into semiconductors (Pearton et al., 2004). Multiferroic materials, which could couple ferroelectric and ferromagnetic parameters, could be used to manipulate spins without magnetic fields (Eerenstein et al., 2006). A recently discovered material of particular interest is graphene—a single monolayer of graphite with unique transport properties (Geim and Novoselov, 2007). The two-dimensional honeycomb lattice of graphene gives rise to a coni- cal band structure that leads to electrons behaving as massless Dirac fermions. Graphene could not only improve FET devices due to its high carrier velocity, but could also enable new devices exploiting its unique physics. The pseudospin property (Min et al., 2008), for example, could potentially enable a correlated shift of charge density between two graphene layers, which could lead to a new low-energy switch. New Methods of Computation: Nonequilibrium Systems Operating an FET at room temperature requires energy barriers of sufficient height to maintain distinguishability between states, which will also be a factor for any other device. One way to get around this problem would be to recapture the computation energy, rather than allowing it to dissipate as heat. This is the goal of adiabatic or “reversible” computation (Bennett, 1988). Another way would be to do out-of-equilibrium computation. In the solid state, local distributions of carriers (or spins or other phase states) can be out of equilibrium with the ambi- ent “temperature” for a period of time before relaxing to the lattice temperature through phonon collisions or other coupling parameters. If the relaxation time is sufficiently long, the potential barriers could be lower, allowing state manipulation with lower switching energy.

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4 QUEST FOR THE NEXT INFORMATION-PROCESSING TECHNOLOGY It has not yet been proven experimentally that either approach can be used for computation with reduced energy dissipation, but out-of-equilibrium behavior is a primary motivation for considering alternative-state variables for informa- tion processing in the first place. If an alternative-state variable obeys the same Boltzman statistics as a dissipative electron-based system, it will have little chance of offering substantial energy advantages over FETs. New Ways of Connecting Devices: Noncharge Data Transfer Any computation system requires connecting multiple devices and transfer- ring information between them. Charge is the natural carrier to use in electron devices, but this is what drives much of the power consumption in modern ICs. An alternative device should transmit the new state variable since converting back to charge would negate any advantage of the new information token. For example, a spin device should transmit spin to the next device, such as through a spin-wave bus (khitun et al., 2007). The movement of a spin wave can be very low energy (Bernevig, 2006), but if electrons must be moved to move the spin, the power advantage is lost. Similarly, if a device uses ferromagnetic or ferroelectric orientation, that should be transmitted through some low-energy magnetic or lattice interaction. Transmitting information short distances by coher- ent waves or collective effects is a promising idea for interconnecting devices, which favors architectures based on nearest-neighbor device coupling. However, it will still probably be necessary to convert to charge for cross-chip interconnects and for coupling back out to the external world. New Methods of Managing Heat: Nanoscale Phonon Engineering Finding more energy-efficient ways to cool devices, given the immediate importance for current CMOS chips, is a very active area of research in the semi- conductor industry. The NRI focus is limited to looking at ways of controlling phonon flow for more efficient phonon extraction and manipulation in device structures. This is being coupled with work on the nonequilibrium system, because finding ways to lengthen the time the state is out of equilibrium with the thermal environment could be key to the development of low-energy computation. It may even be possible to use phonons themselves as the state variable (Wang and Li, 2007). Given the large costs in energy required to lower temperatures, current research is focusing on room-temperature operation. If exceptionally efficient cooling mechanisms were discovered, however, that boundary condition could change.

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0 FRONTIERS OF ENGINEERING New Fabrication Methods: Directed Self-Assembly of Devices Directed self-assembly combines traditional patterning with self-organizing systems to create nanostructures. The ability to fabricate nanoscale CMOS cost-effectively is a challenge for the industry, and the goal of focusing on self- assembly is to improve lithography for continued scaling. NRI work is focused only on self-assembly for the direct creation of new device structures, such as arrays of self-assembled magnetic dots for magnetic quantum cellular automata circuits (Bernstein et al., 2005; Liu and Reinke, 2008). A wider focus on fabri- cation is likely in the future, once the state variable and architecture have been established. SUMMARY The daunting grand challenge of finding a device capable of extending infor- mation processing beyond the ultimate limits of CMOS technology is similar to the challenge faced in the 1940s when solid-state transistors were developed to replace vacuum tubes. The current NRI program (Welser et al., 2008) is largely focused on the first research vector—finding a new device—which would more clearly define directions for research on the other vectors. However, the investiga- tion of alternative devices, data transport, thermal transport, and manufacturability will ultimately have to be tightly integrated to bridge the gap from basic science to a practicable information-processing technology. The CMOS FET is a very efficient switch, and the limits it will approach or reach in the next decade are fundamental to any device operating at room temperature. Although it is difficult to predict what device might be capable of surmounting these limits, a few educated guesses can be made. To reduce power, the new device will probably be slower and will rely on local interconnects. To compensate, it will have to be densely packed and will probably have a three- dimensional architecture. Finally, cost-effective manufacturing will favor uniform arrays of devices—potentially self-assembled—that are robust at the device or architectural level to the increasing variability at the nanoscale. What information-processing architecture is capable of using such a device? The brain, of course, is often cited as a proof of concept that such a device can be found, at least for certain types of applications. The brain is extremely efficient at pattern recognition, for example, but not particularly good at the mathemati- cal computation used in most of our electronic systems today. Hence the quest for a new information-processing technology will require not only finding a new device, but also rethinking how to apply that device and architecture to new appli- cations and products in the future.

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1 QUEST FOR THE NEXT INFORMATION-PROCESSING TECHNOLOGY ACKNOWLEDGMENTS The author gratefully acknowledges the work of the many contributors from industry, academia, NSF, NIST, and other government agencies who worked on this topic in the SIA Technical Subcommittee, the Silicon Nanoelectronics and Beyond working groups, and the ITRS Emerging Research Devices and Emerging Research Materials subgroups. In particular, the author would like to thank G. Bourianoff of Intel and R. Cavin and V. zhirnov of SRC for their contributions. REFERENCES Bennett, C.H. 1988. Notes on the history of reversible computation. IBM Journal of Research and Development 32(1): 16–23. Bernevig, B.A., and S. zhang. 2006. Toward dissipationless spin transport in semiconductors. IBM Journal of Research and Development 50(1): 141–148. Bernstein, G.H., A. Imre, V. Metlushko, A. Orlov, L. zhou, L. Ji, G. Csaba, and W. Porod. 2005. Magnetic QCA systems. Microelectronics Journal 36(7): 619–624. Cavin, R.k., and V.V. zhirnov. 2004. Silicon nanoelectronics and beyond: reflections from a semicon- ductor industry-government workshop. Journal of Nanoparticle Research 6(2): 137–147. Cavin, R.k., V.V. zhirnov, G.I. Bourianoff, J.A. Hutchby, D.J.C. Herr, H.H. Hosack, W.H. Joyner, and T.A. Wooldridge. 2005. A long-term view of research targets in nanoelectronics. Journal of Nanoparticle Research 7(6): 573–586. Cavin, R.k., V.V. zhirnov, D.J.C. Herr, A. Avila, and J. Hutchby. 2006. Research directions and chal- lenges in nanoelectronics. Journal of Nanoparticle Research 8(6): 841–858. Dennard, R.H., F.H. Gaensslen, H.-N. yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc. 1974. Design for ion-implanted MOSFET’s with very small physical dimensions. IEEE Journal of Solid-State Circuits SC-9(5): 256–268. Eerenstein, W., N.D. Mathur, and J.F. Scott. 2006. Multiferroic and magnetoelectric materials. Nature 442(7104): 759–765. Geim, A.k., and k.S. Novoselov. 2007. The rise of graphene. Nature Materials 6(3): 183–191. ITRS (International Technology Roadmap for Semiconductors). 2007. ITRS 2007 Edition. Available online at . khitun, A., D.E. Nikonov, M. Bao, k. Galatsis, and k.L. Wang. 2007. Efficiency of spin-wave bus for information transmission. IEEE Transactions on Electron Devices 54(12): 3418–3421. Liu, H., and P. Reinke. 2008. Formation of manganese nanostructures on the Si(100)-(2x1) surface. Surface Science 602(4): 986–992. Min, H., G. Borghi, M. Polini, and A.H. MacDonald. 2008. Pseudospin magnetism in graphene. Physical Review B 77(041407):1–4. Moore, G.E. 1965. Cramming more components onto integrated circuits. Electronics 38(8): 114–117. Pearton, S.J., W.H. Heo, M. Ivill, D.P. Norton, and T. Steiner. 2004. Dilute magnetic semiconducting oxides. Semiconductor Science and Technology 19(10): R59–R74. Wang, L., and B. Li. 2007. Thermal logic gates: computation with phonons. Physical Review Letters 99(177208): 1–4. Welser, J.J., G.I. Bourianoff, V.V. zhirnov, and R.k. Cavin. 2008. The quest for the next information processing technology. Journal of Nanoparticle Research 10(1): 1–10. zhirnov, V.V., and R.k. Cavin. 2008. Charge of the heavy brigade. Nature Nanotechnology 3(7): 377–378.

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2 FRONTIERS OF ENGINEERING zhirnov, V.V., R.k. Cavin, J.A. Hutchby, and G.I. Bourianoff. 2003. Limits to binary logic switch scaling—a gedanken model. Proceedings of the IEEE 91(11): 1934–1939. zutic, I., J. Fabian, and S. Das Sarma. 2004. Spintronics: fundamentals and applications. Reviews of Modern Physics 76(2): 323–410.