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Modeling, Simulation, Games, and Computing

INTRODUCTION

Ever-increasing computing power over the past 60 years has directly assisted the evolution of modeling, simulation, and games (MS&G), leading to new capabilities for developing models and simulating natural and engineered phenomena with greater realism and accuracy. In the meantime, the desire to model and simulate ever more complex phenomena has driven the demand for greater computing power, creating a feedback loop that has existed since the first computer.

Important shifts have been occurring within the relationship between computing and modeling, simulation, and games. Advances in semiconductor technologies are now delivering a teraflop (1012 floating-point operations per second, or FLOPS) of computing power on a single computer chip, a capability that once required significant infrastructure and was available only to nation-states. As teraflop capability on a chip becomes commercially available, nations and other actor sets will be able to simulate fairly complex phenomena with realistic three-dimensional geometry on desktop systems.

Moving to the next level of sophistication in modeling and simulation (M&S) will require integrating these teraflop chips into different architectures. As such the technological constraints and key technological trends that should be monitored are shifting to other domains—software and the supporting human capital.

This chapter discusses some of the key advances in computation and human capital lying at the intersection of M&S and games that will empower the MS&G of tomorrow. Additional discussion of these advances details potential risks to U.S. leadership and our ability to take advantage of them.



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2 Modeling, Simulation, Games, and Computing INTRODuCTION Ever-increasing computing power over the past 60 years has directly assisted the evolution of model- ing, simulation, and games (MS&G), leading to new capabilities for developing models and simulating natural and engineered phenomena with greater realism and accuracy. In the meantime, the desire to model and simulate ever more complex phenomena has driven the demand for greater computing power, creating a feedback loop that has existed since the first computer. Important shifts have been occurring within the relationship between computing and modeling, simulation, and games. Advances in semiconductor technologies are now delivering a teraflop (1012 float- ing-point operations per second, or FLOPS) of computing power on a single computer chip, a capability that once required significant infrastructure and was available only to nation-states. As teraflop capability on a chip becomes commercially available, nations and other actor sets will be able to simulate fairly complex phenomena with realistic three-dimensional geometry on desktop systems. Moving to the next level of sophistication in modeling and simulation (M&S) will require integrat- ing these teraflop chips into different architectures. As such the technological constraints and key tech- nological trends that should be monitored are shifting to other domains—software and the supporting human capital. This chapter discusses some of the key advances in computation and human capital lying at the intersection of M&S and games that will empower the MS&G of tomorrow. Additional discussion of these advances details potential risks to U.S. leadership and our ability to take advantage of them. 0

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 MODELING, SIMULATION, GAMES, AND COMPUTING FIGURE 2-1 In 1945 the first general-purpose electronic computer was termed the ENIAC and worked principally to solve design problems with the hydrogen bomb. SOURCE: Image courtesy of Los Alamos National Laboratory/Science Photo Library. THE PATH TO ExASCALE COMPuTINg The Evolution of Computing Architectures: From ENIAC to Multicore There has been enormous growth in computing capability over the past 60 years, with an overall performance increase of 14 orders of magnitude.1 Since the inception of the first general-purpose elec- tronic computer, the Electronic Numerical Integrator and Computer (ENIAC), capable of tens of FLOPs (see Figure 2-1), the U.S. computer architecture research agenda has been driven by applications that are critical to national security and national scientific competitiveness. The most dramatic increase has occurred over the past 20 years with the advent of massively parallel computers and associated pro- gramming paradigms and algorithms.2 Computing capability growth over the past 30 years and projec- tions for the next 20 years are shown in Figure 2-2. Through the late 1970s and into the early 1990s, supercomputing was dominated by vector computers. In 1987 a seminal paper on the use of massively parallel computing marked an inflection point for supercomputing (Gustafson et al., 1988). Instead of the very expensive, special-purpose hardware found in vector platforms, commercial off-the-shelf parts could be connected with networks to create supercomputers (so-called Beowulf clusters). Although the programming paradigm for these new parallel platforms presented a significant chal- lenge, it also presented enormous potential. From the mid-1990s through today, massively parallel computers have ridden Moore’s law (Mollick, 2006) to gain more performance for less capital cost. Simulations using greater than 10,000 processors have become routine at national laboratories and supercomputer centers, while simulations using dozens and even hundreds of processors are now routine on university campuses. However, the computing future presents new challenges. The high-performance computing (HPC) community is now looking at several departure points from the past 15 years in order to leverage the increasingly common use of multicore central processing units (CPUs) and accelerators, as projected in Figure 2-2. Exascale initiatives are being developed by several federal agencies, and contracts for 10-plus petaflop computers have been awarded. Notable examples include the National Science Foundation’s (NSF) Blue Waters system located at the National Center for Supercomputer Applications and the National Nuclear Security Administration’s (NNSA) Sequoia system located at Lawrence Livermore National Laboratory. IBM is developing both systems within its Power 7 and Blue Gene product lines, respectively. 1Available from http://en.wikipedia.org/wiki/Supercomputing. Last accessed May 27, 2009. 2Available from http://en.wikipedia.org/wiki/Supercomputing. Last accessed May 27, 2009.

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION 1.E+13 1.E+11 Multicore Era (Peak Estimated Values Plotted) 1.E+09 GigaFlops (1e9 FLOPS) NNSA Sequoia (Est.) 1.E+07 NNSA Roadrunner DOE SC Jaguar 1.E+05 NSF Blue Waters (Est.) Massively Parallel Era (Rmax Values Plotted) 1.E+03 1.E+01 Vector Era (Peak Values Plotted) 1.E–01 1970 1980 1990 2000 2010 2020 2030 Year FIGURE 2-2 Rapid growth in computing capability spanning eras of vector, massively parallel, and future 2-2.eps multicore trends. SOURCE: Vector era and massively parallel era data from Top 500 (http://www.top500.org/); multicore era data notional based on aggressive growth. Multicore Processing As component sizes continue to shrink while the processing speed of a CPU remains almost constant, vendors are adding additional processing units to a single chip, creating a new form of parallelism. Each of the processing units is termed a core; one example of a multicore chip is shown in Figure 2-3. Addi- tional performance for a “processor” is being obtained by adding more cores, as shown in Figure 2-2. However, as demonstrated in Figure 2-4, clock frequency appears to be asymptotic, though the actual upper bound is still unknown. Multicore processors are currently achieving speeds higher than 3 Ghz. Perhaps the most dramatic example of multicore chip technology was Intel’s demonstration of a teraflop (1012 FLOPS) on a chip in 2007 (Figure 2-3). This remarkable achievement is clearly demon- strated when compared to the first teraflop computer, the NNSA’s Advanced Simulation and Computing (ASC)3 program Red Storm platform. The Intel processor is about the size of a dime and consumes 62 watts of power. A decade earlier, a peak teraflop of computing power required 2,500 square feet and consumed half a megawatt of power. However, there is still much progress to be made to get the work performed on the Red Storm platform translated to the Intel chip or its counterparts, principally due to the limitation of the memory subsystem delivering data to the processor. While processors have doubled in performance approxi- mately every 18 to 24 months in accordance with Moore’s law, memory speeds have increased at most 3ASC is the abbreviation for the collaborative Advanced Simulation and Computing Program across Department of Energy (DOE) national laboratories to ensure the safety and reliability of the nation’s nuclear weapons stockpile. Available at http:// www.lanl.gov/asc/about_us.shtml. Last accessed June 15, 2009.

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 MODELING, SIMULATION, GAMES, AND COMPUTING FIGURE 2-3 Intel’s 1 teraflop on a chip (275 mm2 and 62-watt power consumption), dem- onstrated in 2007. This single chip contains 80 cores, hence the term “multicore.” SOURCE: See http://techresearch.intel.com/articles/ Tera-Scale/1449.htm. Accessed May 27, 2009. Reprinted with permission of Intel Corporation. 10 percent per year. This has been termed the “memory wall” (Wulf and Mckee, 1995). A fundamental reason for this slowed increase in memory speed is that, with present memory chip design, increased clock frequency results in increased power consumption (i.e., transistor leakage current increases with increasing clock frequency). The mismatch between CPU and memory speed has meant that many applications, especially those in the national security arena, have been getting less and less of the peak performance from next-genera- tion CPUs because the algorithms for many national security applications do not reuse the data in cache. Rather than ride Moore’s law, these applications’ performance increases are instead trending along the speed increases realized in memory systems. For example, in finite element simulations, very few bytes in a cache line are used once, much less multiple times, before writing back to memory. Overall, studies have shown that for many national security applications the processor spends the majority of its time doing integer arithmetic to determine memory locations (Moore, 2008). Finding 2-1: “Cache-friendly” algorithms have been developed, but many take longer to run than “non- friendly” algorithms. For intelligence analysts responsible for technology warning, a major breakthrough in memory speeds would be a game changer and have significant national security implications. One

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION 10000 ��� Frequency (MHz) � � quad core dual core 1000 � � � 100 � 10 1990 2010 1995 2000 2005 FIGURE 2-4 Clock speed in terms of frequency versus year. All data except those labeled refer to single-core processors. Even with additional cores added to a chip, the chip clock speed has currently reached an asymptote. SOURCE: Dunning (2009). 2-4.eps area showing promise is three-dimensional packaging of the memory and CPU, which provides for more pins, and thus higher bandwidth, to be connected between the two devices (kogge et al., 2008). Rather than monitoring advances in processor speeds, tracking improvements in memory speed could provide earlier warning of the next step change in capabilities. This technology assessment is summarized in Chart 2-1. CPu Accelerators: graphical Processing units Computer vendors are now exploring adding accelerators to CPUs, reminiscent of the vector era of computing in the 1980s and early 1990s (see Figure 2-2). The accelerator area has been dominated by the fast-paced gaming industry. Driven by the gaming community’s appetite for faster and better three-dimensional graphics rendering, the computer industry has responded with unprecedented speed increases through graphics accelerators (NRC, 1997; Dunning, 2009). Graphical processing units (GPUs, or graphics processors), a core technology for video-intensive games, are greatly outpacing commodity processors, as shown in Figure 2-5. Multicore GPU chips include the 240 cores on the $300 Nvidia graphics processor sold today with many desktops and laptops. The floating-point capability of Nvidia’s, GPUs is almost four times that of the most powerful com- modity CPU for the cheapest GPU, and newer GPUs such as Nvidia’s Tesla S10704 are providing many 4Available at http://www.nvidia.com/object/product_tesla_s1070_us.html. Last accessed June 16, 2009.

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 MODELING, SIMULATION, GAMES, AND COMPUTING CHART 2-1 Collapsing the Memory Wall Technology Observables A successful breakthrough in memory speed (and Memory speed: Rather than ride Moore’s latency) will entail increased memory clock frequency law for ever-increasing processor speeds, without associated increased power consumption. many applications’ performance increases are instead following the speed increases realized in memory systems. A major breakthrough in memory speeds would be a game changer and have significant national security implications. Some applications could run 10 to 50 times faster. In the hands of an adversary, they could leapfrog the United States in simulation capability by 5 to 7 years. Accessibility Maturity Consequence Level 2 Technology watch Given notable increases in memory speeds, a greater fraction of theoretical peak performance can be achieved. With existing parts at existing speed but without the memory wall, a two- to threefold improvement would be possible. 400 1.50 GHz G80 NVIDIA (GPU) 350 INTEL (CPU) 1.35 GHz G80 300 250 Gflops 200 150 2.66 GHz Quad-core 100 3.4 GHz Dual-core 50 0 2002 2003 2004 2005 2006 2007 FIGURE 2-5 GPUs, a core technology for games, are greatly outpacing commodity CPUs. SOURCE: Dunning 2-5.eps (2009).

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION FIGURE 2-6 NNSA’s ASC Roadrunner supercomputer was the first general-purpose supercomputer to reach a sustained petaflop. SOURCE: LeRoy N. Sanchez, Records Management, Media Services and Operations, Los Alamos National Laboratory (http://www.lanl.gov/news/index.php/fuseaction/home.story/story_id/13602). Image courtesy of Los Alamos National Laboratory. times greater performance. This trend is likely to continue, and commodity processor companies, such as Intel, have taken notice by investing in competing technologies such as Larrabee (Intel Corporation, 2008). As programming models and languages (e.g., Nvidia’s CUDA5) evolve for GPUs, unprecedented performance gains will be realized for scientific software in the near future. Already, hundreds of scientific software applications that are inherently data parallel and can take advantage of multiple cores have been ported to GPUs running CUDA, with speed-ups ranging from factors of 2 to a thousand.6 Factors of 10 have huge impacts on scientific code, since larger systems and/or longer timescales can be accessed—often the difference between solving a problem and not solving it. Factors of 100 are game changing, enabling wholly new scientific questions to be addressed that were outside the typical capabilities available to many scientists. With factors of 100 to 1,000 in speed-up, state-of-the-art, three-dimensional scientific simulations that previously required an expensive supercomputer can be done on a desktop computer costing only a few thousand dollars or less. Financial analysis, medical imaging, computer vision, bioinformatics, materials design, real-time ray tracing, and virtual worlds will all greatly benefit from these trends. Accelerators can, with significant effort, be programmed to solve scientific problems. Two examples of this can be found with the Sony PlayStation 3 (PS3). The Folding@home distributed computing program (Snow et al., 2002) uses Sony PlayStations throughout the world, contributed freely by their owners, to perform protein folding around the clock. This extremely latency-tolerant software exploits unused gaming cycles to advance biological science. Another example of PS3s advancing research is the ASC Roadrunner system, the first petaflop (1015 FLOPS) platform, shown in Figure 2-6. In this case, a tightly integrated, massively parallel platform was constructed with Advanced Micro Devices dual-core 5See http://www.nvidia.com/object/cuda_home.html. 6See http://www.nvidia.com/object/cuda_home.html#state=filterOpen;filter=Science.

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 MODELING, SIMULATION, GAMES, AND COMPUTING Opterons, where each core has two IBM Cell processors (the same processor type as found in Sony’s PS3) attached as accelerators. Although the Roadrunner system represents an impressive capability, the processor architecture represents a significant design departure from the past 20 years and will require significant rewriting of national security applications to take advantage of the accelerators. CPu Accelerators: Field-Programmable gate Arrays Field-programmable gate array (FPGA) technology has found its way into the HPC market. The attraction of FPGAs is their electrical efficiency given their potential computing power. For example, the Xilinx V5LX330 is rated at 60 gigaflops and consumes only 15 W. As a comparison, the Intel Wood- crest processor (a two-core system) is rated at 48 gigaflops but consumes between 80 and 130 W. 7 The FPGAs obtain this performance through configurable logic—the same silicon can be reconfigured on the fly to support different operations and thus pipelining. kernels of key national security algorithms have greater than 10 times and in some cases greater than 100 times increased performance. Harnessing these performance gains is limited due to an FPGA programming model that typically requires rewriting applications in hardware description language. Higher level language support is an active research area, and many universities and U.S. national laboratories have research programs to investigate the use of FPGAs for scientific applications, including creating HPC architectures that attach FPGAs as accelera- tors to the main processor. Roadmap for Future High-Performance Computing The high-performance (supercomputing) computer architecture research agenda in the United States, with stewardship falling primarily to the Department of Energy and the Department of Defense (notable programs include the NSF Blue Waters and the NNSA Sequoia systems previously described), will continue to be driven by applications that are critical to national security and national competitiveness. This leadership territory is no longer ours alone, and trends indicate that more countries will compete for the top 10 platforms in the future. Over the past 10 years, the United States has owned 50 percent or more of the top 500 supercomputers.8 However, in November 2007, four systems in the top 10 were outside the United States, including a surprising entry from Indian commercial company Tata Sons. In November 2008, China joined the top 10 list with a system from Dawning. The take-away point from these two examples is that leading-edge HPC is now being pursued by the global commercial sector. The U.S. government and HPC industry have competition. As described in a recent international assessment of simulation-based engineering and science by the World Technology Evaluation Center (WTEC, 2009), the world of computing is flattening, and any country with interest and minimal resources can have access to HPC. Several countries have the tech- nology, resources, and desire to be first to achieve exaflop (1018 FLOPS) computing. Japan, Germany, France, and China are all committed to HPC, with ready access to world-class resources, faculty, and students. Germany is investing nearly U.S. $1 billion toward next-generation HPC hardware in partner- ship with the European Union (WTEC, 2009). Japan has always been a leader in HPC, and as the first to achieve 40 teraflops in the past decade with the Earth Simulator built by Japanese computer company NEC, Japan has an industry-university-government roadmap to reach exascale computing by 2025. In a recent turn of events, however, NEC and Hitachi, two of the three major vendors leading the develop- 7Available at http://rssi.ncsa.uiuc.edu/docs/industry/Xilinx_presentation.pdf. Last accessed May 27, 2009. 8Available at http://www.top500.org/. Last accessed June 22, 2009.

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION ment of Japan’s Life Simulator (or Kei Soku Keisanki—a 10-petaflop computer planned for 2010-2011 to leapfrog past Blue Waters) pulled out of the partnership because of the 2009 global financial crisis which has caused huge losses and massive layoffs. This announcement leaves Japan’s next-generation supercomputing project and its future HPC roadmap in question (Feldman, 2009). An NEC press release from May 2009 reads: NEC estimated that costs for moving forward with the manufacturing phase of the Next-Generation Su- percomputer Project would significantly impact earnings for the fiscal year ending in March 2010, due to extensive investment required for the computer’s manufacturing. Therefore, NEC has decided not to participate in the project’s manufacturing phase. . . . NEC will now contribute to the project through the application of new vector architecture and optical interconnect technologies completed during the design phase, in addition to architectural research for rapid computing, development, education and operational support for application software with universi- ties and research institutions. (NEC, 2009) Without NEC and Hitachi as full partners, the future of Fujitsu’s SPARC64 VIIIfx chip (the 128- gigaflop scalar processor it had been developing for the Life Simulator and HPC in general) also is in question. According to an HPCWire report (Feldman, 2009), the new Sparc chip, code-named Venus, is an eight-core CPU with an embedded memory controller and enhanced SIMD (single instruction, multiple data) support. The report describes claims by Fujitsu that the Venus prototype delivers more than double the raw floating-point performance of the Intel Nehalem processor while consuming much less power. However, without the partnership of NEC and Hitachi, support of the chip’s development by the Japanese government is unclear. With no domestic computer vendors committed to petascale computing and beyond, the Japanese government and RIkEN (the government-funded research agency charged with leadership of the petascale computing project) will look to international partnerships to fulfill or redefine their roadmap. Software applications will continue to evolve, in many cases rewritten to take advantage of petascale multithreaded platforms. Following the direction of Internet commerce, the M&S user space is expected to migrate toward virtual desktops. This is principally due to the reduced cost of managing application solutions. Application environments are anticipated to become like Google searches, with the computing infrastructure hidden from the user (e.g., cloud computing). Increased network connectivity, the pres- sure to lower costs, and highly replicated worker stations continue to drive globalization of software development and analysis teams. Such advances will eventually make access to petascale computing relatively ubiquitous, potentially enabling breakthroughs in a broad range of science and engineering disciplines, including molecular science, weather and climate forecasting, astronomy, earth sciences, and health (Ahern et al., 2007), and business and commerce. The pace of the next major leap in computing power, an exaflop computer, will be significantly chal- lenging to accomplish in a cost-effective and scalable way. The top obstacles are power consumption, resilience, the memory wall (Chart 2-1), and scalability. kogge et al. (2008) discuss these areas in great detail. Using computer vendor roadmaps suggests that an exaflop computer would require finding 10 3 to 104 times more parallelism in existing applications, hundreds of megawatts of power, and a mean time to failure of only a few minutes. Power requirements and resiliency obstacles are a significant challenge and will need to be resolved by the HPC industry with government-supported research and development. Finding the increased levels of parallelism for strong scaling will require new approaches to the underlying algorithms. Strong scaling holds the problem size fixed and improves computational speed by increasing the number of processors used to solve the problem, while weak scaling allows the problem size to increase by increasing the number of processors. In the era of teraflop to petaflop computing,

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 MODELING, SIMULATION, GAMES, AND COMPUTING weak scaling has dominated because of the requirement of realistic, numerically converged, three-dimen- sional simulations. In addition, for much of this era the processors were single-core chips and increased processing speeds provided much of the increased HPC capability. In exaflop computing, strong scal- ing, which improves computational speed, will be an important consideration for many time-dependent applications, as opposed to weak scaling that improves the ability to process larger problems. Finding 2-2: Exaflop-level computing is expected to be aggressively pursued by the United States, Europe, and Asia (WTEC, 2009). Areas for intelligence analysts responsible for technology warning to watch that could facilitate a breakthrough for usable exaflop computing include technologies that: • Significantly reduce memory power consumption; • Dramatically increase memory-to-processor communication speed while reducing latency; • Dramatically increase processor-to-processor communication speed while reducing latency; • Dramatically reduce part counts through integration or packaging that will increase the mean time to failure; or • Automatically generate scalable code. Software for Exascale Computing Expertise in writing scientific applications for massively parallel architectures is fairly limited and even more limited for accelerators like GPUs and FPGAs. Programming models, libraries, and compilers that automate parallelization and threading of sequential code would open these future HPC platforms to a broad set of application developers. Automated parallelization has been a holy grail of HPC since the appearance of autovectorizing compilers in the 1980s. For example, the Portland Group, Inc., is working on a compiler with open multiprocessing-like options that will autogenerate CUDA (Compute United Device Architecture) kernels from loops.9 Although there are limitations, this work is a first step in the direction of compilers that may eventually enable nonexperts to obtain blazingly fast speeds on many applications. High-level scripting languages (such as Python) that could be compiled to a GPU kernel would also make these accelerators more accessible to a wider range of users. Already, any programmer familiar with MATLAB, a popular computing environment used by university students around the world, can easily access the power of a GPU. Using a program called Jacket made by AccelerEyes, which runs under MATLAB (created by MathWorks), just a few changes to MATLAB m-files will cause the com- putationally expensive parts of the code to run on the GPU.10 With well over 100 million CUDA-enabled Nvidia GPUs deployed worldwide in laptops and desktops,11 such breakthroughs could have important national security implications (see Chart 2-2). Algorithmic advances will be another key to sustained exascale computing. Improved algorithms have resulted in performance gains of several orders of magnitude in many application domains (keyes et al., 2003, 2004), providing speed-ups that in some cases far surpass Moore’s law with a doubling of performance every eight, rather than every 18, months (WTEC, 2009). An example of the role of algo- 9A loop in computer science is “a sequence of instructions that repeat either a specified number of times or until a particular condition is met,” as defined at http://www.answers.com/loop. A description of this CUDA kernel generation process is avail- able at http://www.pgroup.com/resources/accel.htm. Last accessed June 15, 2009. 10Available at http://www.mathworks.com/products/connections/product_detail/product_35939.html. Last accessed June 3, 2009. 11Personal communication between David kirk and Committee Member Sharon Glotzer on July 16, 2009.

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0 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION CHART 2-2 Software for Massively Parallel Architectures Technology Observables Expertise in writing scientific applications Monitor international HPC conferences and open- for massively parallel architectures is source software distribution sites for programming currently fairly limited and even more limited models, libraries, and compilers that automate for accelerators like GPUs and FPGAs. parallelization and threading of sequential code. Experience programming explicit data movement technologies (e.g., vectors) is even more limited. Accessibility Maturity Consequence Level 2 Technology watch The ability to easily write applications for massively parallel architectures will open future HPC platforms to a broader set of application developers (e.g., Google, MATLAB). rithms versus hardware in achieving major performance gains is highlighted in the ITER 12 Roadmap authored by Stephen Jardin (Princeton University) and David keyes (Columbia University) (Sipics, 2006). According to a recent international study on simulation-based engineering and science (WTEC, 2009), to simulate the dynamics of ITER for a typical experiment would require computers with 10 24 FLOPS. The Jardin-keyes roadmap proposes how the 12 orders of magnitude required to bridge this gap can be achieved from today’s teraflop computers: . . . three orders of magnitude will be gained through hardware, with both processor speed and increased parallelism contributing equally; the other nine orders of magnitude will come from algorithms (soft- ware), namely four orders due to adaptive griding, three orders due to implicit time-stepping, one order due to high-order elements, and one order due to the reformulation of the governing equations in field-line coordinates. (Sipics, 2006) The algorithmic advances attained in this fusion example will benefit the larger scientific community far beyond the fusion community. This example demonstrates the need for algorithmic advances in HPC in addition to hardware advances for modeling and simulation. The key role that next-generation algorithms will play in achieving peta- and exascale computing implies that this domain will require close watch in order to determine potential breakthrough capabili- ties. The committee notes though that tracking advances in algorithm writing is significantly harder than tracking advances in hardware development. Future Technologies Enabled by Exascale Computing A study by Oak Ridge National Laboratories (Ahern et al., 2007) examined the potential scientific discoveries enabled by exaflop computing. A partial summary of that study’s results is given in Table 2-1. 12ITER is an international research collaboration for fusion energy.

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 MODELING, SIMULATION, GAMES, AND COMPUTING TABLE 2-1 Summary of a Study that Examines the Potential Scientific Discoveries Enabled by Exaflop Computing Science Driver Science Objective Impact Understand synthesis of alloy Define the thermodynamics Magnetic data storage; nanoparticles with potential of compositions of alloy economically viable ethanol impact for design of new nanoparticles production; energy storage catalysts via structural transitions in nanoparticles Climate decadal climate Cloud-resolving (1-5 km) Understand and prepare for prediction atmosphere; longer time committed climate change integration (100-300 years, 1,000-year spin-ups); larger ensembles (5-20) Dynamical linking of Couple infrastructure, climate, Identify future energy socioeconomic and climate demographic, informational, infrastructure needs responses and energy economic models to predict adaptation as communities react to stresses on infrastructure systems and propose potential policies Systematic, large-scale Combine density functional Virtual design of catalysts and exploration of optimal theory with evolutionary separating agents materials for catalysis or search for complex materials nuclear materials separation or an accurate combinatorial agents approach to screen the best separation material out of O(103) compounds SOURCE: Oak Ridge National Laboratory. HuMAN CAPITAL IN SCIENCE-BASED MODELINg AND SIMuLATION There is a profound lack of highly skilled computational scientists and engineers able to fully leverage the current HPC state of the art (Benioff and Lazowska, 2005; see also WTEC, 2009, and references therein), creating large-scale concern for a skilled scientific workforce capable of exploiting next-generation petaflop and exaflop systems. One major finding in a recent international assessment of simulation-based engineering and science (SBE&S) is as follows: Inadequate education and training of the next generation of computational scientists threatens global as well as U.S. growth of (the discipline of) SBE&S. This is particularly urgent for the United States; unless we prepare researchers to develop and use the next generation of algorithms and computer architectures, we will not be able to exploit their game-changing capabilities. (WTEC, 2009) M&S is prevalent in every discipline and subdiscipline of science and engineering. Some fields, such as aerospace engineering and atmospheric science/climatology, have been totally transformed by computer simulation (Oden et al., 2006). At most major universities, students have access to a variety of courses in computational science and engineering, but many key topics related to “programming for performance” fall between the cracks, and much of the skill needed to program state-of-the-art super-

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION computers is still learned primarily through peer-to-peer learning and apprenticing. Strictly speaking, HPC is not computer science, yet it is also not a domain science. Thus from a curriculum standpoint, the core competencies of the multidisciplinary HPC field are often orphaned as neither computer science nor computer engineering, or other departments have direct responsibility for them. With new accelerator and multicore architectures, this lack of formalized curriculum is even more prevalent. Examples of core competencies for HPC include but are not limited to the following (Glotzer et al., 2009): • Alternative architectures utilizing FPGAs and GPUs; • Multicore/many-core/massive-multicore computer architectures for scientific computing; • Modern languages and application programming interfaces for multicore architectures; • Programming for performance (compilers, caches, networks, memory latency, throughput, and addressing, etc.); • Debugging, performance, and validation tools; • Big data input/output, storage, analysis, and visualization; • Co-processor and acceleration utilization for scientific applications; • Application development environments and application frameworks; • Modern software engineering; • Validation, verification, and uncertainty quantification; and • Systems design, program management, testing, systems management, and systems maintenance. In the late 1980s and early 1990s many universities created interdisciplinary certificate programs (and a few have since created Ph.D. programs) in computational science and engineering to address, in many cases successfully, the education and training gap that existed then. Many of those programs persist today. However, as the pace of computer architecture development has quickened, many of these programs have not evolved sufficiently, and faculty, students, and employers alike are frustrated by the limited M&S skills learned by scientists and engineers (WTEC, 2009). Furthermore, many universities lack a critical mass of expertise at the leading edge of HPC today. As a consequence, there is general consensus among faculty and employers around the world that today’s computational science and engineering students are ill-prepared to create and innovate the next generation of codes and algorithms able to utilize new supercomputing architectures (including accelerators and multicore processors; WTEC, 2009). The WTEC report also gives evidence that this lack of proper preparation begins in high school (or earlier) and continues through graduate education and beyond. Obviously in graduate school, increased topical specialization without concomitant depth in computing know-how further exacerbates this. In short, there is a clear and widening gap between what today’s students learn vis-à-vis HPC and what they need to know to develop scientific codes for massively parallel computers and/or multicore architectures, including the graphics processors developed for the gaming industry and beginning to be used in science and engineering applications. Instead, it is generally thought that students use codes primarily as black boxes, with only a very small fraction of students learning proper algorithm and software development skills. Students receive no real training in software engineering for sustainable codes and little training in uncertainty quantification, validation and verification, or risk assessment, which is critical for decision making based on modeling and simulation. These human capital issues may pose a potential threat to the United States by exploiting HPC for modeling and simulation in new and novel ways. Without addressing the threat, U.S. capabilities in terms of prediction and assessment will be limited both on the battlefield and off. As computers have become faster, models have increased in fidelity, causing games to become more realistic and accurate. Second, the increasing fidelity of games has led game makers to seek the manufacture of higher-performance

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 MODELING, SIMULATION, GAMES, AND COMPUTING computer chips. As such, the need for a skilled workforce in M&S, and in simulation-based engineer- ing and science generally, will become increasingly important to national security to take advantage of improvements in speed and accuracy (Benioff and Lazowska, 2005; SIAM, 2001; SIAM, in press). HuMAN CAPITAL IN COMPuTER AND vIDEO gAMES While there is declining academic investment in high-performance computing, game design and development in the meantime together are becoming a new and accepted academic discipline worldwide, creating new interdisciplinary paradigms that will touch on computer science, simulation, and related disciplines. This is expected to create not only new consumer applications but also the “serious” gaming applications discussed in Chapter 3 (Iuppa and Borst, 2006). Historically, the computer games industry began in the late 1970s as a hobbyist activity. Given the primitive state of microcomputers and graphics then, most games during the earliest days could be designed, developed, and produced by a single programmer working at home. These individuals were typically self-taught, working in a range of early microcomputer languages, including assembler, Pas- cal, and BASIC. The growth of the gaming market in the 1990s included larger audiences demanding more sophis- ticated products, increased computational and graphics power in the home, and ultimately the rise of multiplayer games using large-area networks or the Internet. Collectively, these changes had several implications for the way games were created. First, larger development teams had to be deployed. From the solo developer in the 1980s industry, the process grew to include literally hundreds of contributors for “A list” titles in the early 2000s. In a growing industry, this meant that both the budgets for individual game titles were growing exponentially and that talent had to be sourced and managed worldwide. In the 1980s, it cost tens of thousands of dollars to develop a game; in the 1990s, it cost millions; now it costs tens of millions. 13 Second, these teams had to be organized among individuals with skill sets that previously would not have worked together. A partial list of professional categories typically included in a single project is given in Box 2-1. Note that this list does not include the substantial studio or publisher overhead in the form of execu- tive oversight, sales, marketing, public relations, and so forth. The cost to develop a top-line release from a major publisher increased from $50,000 in 1980 to $10 million or more in 2009 (Dobra, 2009). Not only has the risk become higher, but the need for talent, skilled management, reliable production processes, and controls, is also greater. Ironically, the rise in mobile gaming and casual Web-based gaming has introduced a contrapuntal trend, as many mobile games and Flash-based browser games can be developed and launched online by one or two developers for a few tens of thousands of dollars. These games are typically free to play and supported, if at all, by advertising and micropayments from users. 14 Furthermore, casual gaming environments are increasingly mobile, socially networked, and enabled by products such as the iPhone/ iTouch, which offers a large ubiquitous platform, leading to this form of gaming becoming increasingly viral in nature. While the early games industry was able to build up a pool of accomplished developers and its early culture tended to foster informal transfer of knowledge to new entrants, the need for scalability in 13See, for example, http://www.411mania.com/games/news/121194/Cost-to-Develop-Gran-Turismo-5-Now-at-60-Million- Dollars.htm. Last accessed November 13, 2009. 14This “contrapuntive trend” is not unlike that between $200 million petascale computers and $200 GPUs, both of which will revolutionize science and engineering simulation.

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION BOX 2-1 Partial List of Professional Categories Typically Included in a Single Game Development Project Actors Game designers Voice-over talent Game producer (and assistant producers) Scripting (game-level scripting) Writers Dialogue Director of engineering Video producer Technical directors Video editors Software engineers Sound engineers Graphics engineers Musical director Sound engineers Musicians Technical art director Tools development lead Lead art designer Tools developers Three-dimensional artists Tools quality assurance Animators Multiplayer engineering lead Two-dimensional artists Multiplayer engineers Cut-scene artists Operations director Character artists Operations personnel (for online play) Motion capture technical lead Quality assurance (typically 100 or more Motion capture artists Motion capture engineers individuals worldwide SOURCE: Call of Duty 4 credits found at http://www.mobygames.com/game/ps3/call-of-duty-4-modern-warfare/credits. Accessed June 19, 2009. managing knowledge by the industry inevitably led to the formation of academic programs in games. These programs tend to fall into four categories: • Computer science programs in game development; • Humanities-oriented programs in game design and management; • Media studies programs that research the impact of video games on individuals and society; and • Trade school programs that prepare students for many of the other skills needed to enter the games industry (such as three-dimensional modeling, scripting, Web design, user interface design, sound effects, and music). In 2000 the Independent Game Developers Association (IGDA) began a program to assess the state of emerging academic activity in game-related programs at universities worldwide. The purpose of this ongoing initiative “has been focused on setting curriculum guidelines, to enhance collaboration between industry and academia and to provide guidance to students wanting a career in games.” 15 In February 2008 the IGDA’s Game Education Special Interest Group released a document entitled IGDA Curriculum Framework: The Study of Games and Game Deelopment to assist academics and their institutions in establishing one or more undergraduate and graduate programs. The document provides 15Available from http://www.igda.org/academia/. Last accessed June 3, 2009.

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 MODELING, SIMULATION, GAMES, AND COMPUTING TABLE 2-2 Number of Institutions Offering Postsecondary Courses and Degrees in Game Studies as of March 2009, by Country Number of Number of Country Institutions Country Institutions United States 161 Colombia 2 Canada 49 Japan 2 United kingdom 43 Norway 2 Australia 21 Switzerland 2 Sweden 10 Turkey 2 India 9 Argentina 1 Germany 6 Belgium 1 Brazil 5 Chile 1 France 5 Greece 1 Denmark 4 Hong kong 1 Malaysia 4 Israel 1 Mexico 4 Italy 1 Singapore 4 korea 1 Spain 4 New zealand 1 Austria 3 Pakistan 1 Finland 3 Serbia and Montenegro 1 Ireland 3 South Africa 1 Netherlands 3 Taiwan 1 China 2 Thailand 1 TOTAL 367 SOURCE: Game Career Guide. a generalized framework that outlines core topics (e.g., game programming, game design, business, critical game studies), degree programs, and institutional considerations for adoption of game-related courses and degrees. As of March 2009 there were over 160 four-year undergraduate and graduate institutions in the United States that offer courses and/or degree programs in a range of game-related studies. Notable universities with comprehensive programs include the University of Southern California (with degree programs in both the computer science and cinema departments), Carnegie Mellon University, the Massachusetts Institute of Technology, the University of Michigan, Michigan State University, and the Rochester Institute of Technology. International Presence Overseas interest in academic programs for game development is increasing accordingly. Accord- ing to lists maintained by the Game Career Guide,16 there are well over 200 institutions in 37 countries offering a range of postsecondary courses and degrees in game studies. The breakout by country is listed in Table 2-2; breakout by region is listed in Table 2-3. These data evidence that game development is no longer just a phenomenon of the Western and English-speaking world. English-speaking countries still dominate the academic games programs, with the United States, United kingdom, Canada, and Australia dominating the field. Given the rise of the commercial game 16See http://www.gamecareerguide.com/schools/. Last accessed May 7, 2009.

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 THE RISE OF GAMES AND HIGH-PERFORMANCE COMPUTING FOR MODELING AND SIMULATION TABLE 2-3 Number of Institutions Offering Post- Secondary Courses and Degrees in Game Studies as of March 2009, by Continent Region Total Schools North America 210 Europe 92 Asia 48 Central and South America 13 Near East 3 Africa 1 TOTAL 367 SOURCE: Game Career Guide. market in Japan and China, however—and noting its strong orientation toward online games (Mulvenon, 2008)—further growth can be expected in academic game programs in these countries. Industry Implications of Formal Academic game Programs Given that there are several different areas of game curriculum (game design, game technology, trade school skills, game studies, and criticism), the effects of game curriculum programs on the games industry, and ultimately on the market and even national security, will be difficult to predict. Neverthe- less, a few hypotheses seem plausible. Games curriculum programs today are like computer science and engineering programs in the 1990s. There are now hundreds of such programs, both formal and informal, throughout the United States. Traditionally, development knowledge in the games industry was handed down from person to person in an informal mentor-apprentice fashion, usually as the result of working together on a project team. Formal computer science disciplines (such as artificial intelligence) were injected into specific games on an ad hoc basis. Games curriculums are likely to become more mainstream in universities as the specialty expands in understanding and professional membership. These programs are likely to improve overall rates of innovation as the membership and supporting community gain mass. Because many game design/technology programs have a strong orientation toward project output (one University of Southern California graduate student’s game flOw was the most downloaded game on Sony’s PlayStation 3 network as of May 2008 (Sheffield, 2008), we are also likely to see a range of games produced that are not necessarily rooted in commercial entertainment needs. In particular, with academia’s ability to attract government and foundation funding, there are already signs that college and university students are producing an increasing number of serious games—games that have explicit pur- poses such as learning, training, or deeper understanding of a specific subject through interactive play. While formalized university training and popular games or hits are not necessarily correlated (or researched at this time), there is reason to believe that the university route to success in games is begin- ning to take hold. Valve’s Portal game was sourced from a university project. Sony’s Cloud game was originally a USC student project, and the development studio ThatGameCompany is staffed heavily with USC and Northwestern University graduates. As stated, there is no empirical evidence that such training is leading to a higher level of hits. Major publishers and developers are increasingly in need of highly talented developers and are sourcing them through universities as it is seen as fairly efficient even if additional training is needed. What may actually be driving university-based success though is not just the education but the fact that at such programs students have increased access to resources, time, peers,

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 MODELING, SIMULATION, GAMES, AND COMPUTING and mentorship devoid of commercial pressure to work on new ideas and forms of games. The better university programs also place strong emphasis on developing new theories and approaches to games that might not get the same cultivation within commercial game development. Thus, it is a combination of self-selection of talent into game programs and stronger education and mentorship, coupled with the environment that universities create, that is potentially turning them into potent incubators of talent and new games. Almost all game development kits being produced now have application programming interfaces that allow access and the sharing of information via Facebook. For example, the iPhone SDk incorporates this feature, and many university students now build games connected to Facebook. This development will likely continue; an important issue will be whether Facebook has been designed with any scalability to take on this increasing burden. Second, further exploration of neuroscience research on the ways in which the brains of frequent gamers are noted to function differently with regard to perception, speed of response, and multitasking will be important. There are now companies focusing on low-cost hybrid EEG (electroencephalogram) sensors for interacting with and analyzing games and players (e.g., EmSense, NeuroSky, Emotiv). The biggest push for brain sensing is coming from advertisers who want to know what the consumer thinks of the way they advertise their brands. FINAL THOugHTS Advances in computing technologies up to the teraflop level have yielded the raw computing power required to model and simulate fairly complex phenomena relatively ubiquitously. A threshold has been crossed where M&S capabilities that were once the province of nation-states and the more technologi- cally sophisticated are now global and available to any and all actors. It is clear that no one society can maintain a sustainable, strategic, comparative advantage of access to these capabilities. The next level of computing capability—petascale and exascale computing—will require new architectures with interesting implications for anyone concerned with the monitoring of technologi- cal progress. The use of massively parallel and multicore architectures raises algorithm and software development, rather than the development of hardware, as the key barriers to overcome. In fact, the demand for ever more powerful processors by the games and visual computing industry in order to deliver ever higher fidelity images is driving the evolution of much of the hardware (NRC, 1997). Less well understood is what advances in algorithms and software are needed to take advantage of massively parallel, multicore-based architectures, let alone who is training the human capital that will produce these advances. From a technology watch perspective, this implies that, to progress to exascale computing and beyond, a shift in relative focus and resources may be in order, from tracking the progress in hardware development to that of algorithm/software development and human capital development. The fact that this latter goal is a fundamentally harder challenge is noteworthy. REFERENCES Published Ahern, S., Sadaf Alam, Mark Fahey, Rebecca Hartman-Baker, Richard Barrett, Ricky kendall, Douglas kothe, O. E. Messer, Richard Mills, Ramanan Sankaran, Arnold Tharrington, James B. White, and the Computing Requirements Team of the National Center for Computational Sciences. 2007. Scientific Application Requirements for Leadership Computing at the Exascale. Oak Ridge, TN: Oak Ridge National Laboratory. Available at http://www.nccs.gov/wp-content/media/ nccs_reports/Exascale_Reqms.pdf. Accessed May 27, 2009.

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