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OCR for page 61
6
Device Testing for High-Temperature
Electronic Materials
This chapter concentrates on devices made from
silicon and silicon carbide, as these are the two materials
systems for which the most data are available. The data
are encouraging and suggest that electronic systems based
on either of these two materials will operate successfully
at elevated temperatures.
There are three areas of testing that are discussed in
this chapter: (1) short-term, constant-temperature tests, (2)
constant-temperature life tests, and (3) thermal-cycling
tests. The short-term and constant-temperature tests are
encouraging. There is no known thermal-cycling data,
however, and more research is required. A few comments
at the conclusion of the chapter are devoted to the subjects
of packaging and future testing
SHORT-TERM
CONSTANT-TEMPER\TURE TESTS
Short-term constant-temperature tests are the first type
done on each device intended for use at elevated
temperatures and thus the one test for which there is the
most data. In a typical test of this kind, a device or
integrated circuit is placed in a test fixture that can be
varied in temperature. Often, the device under test is also
in a special, controlled environment, such as dry nitrogen
or vacuum.
Figures 6-1 and 6-2 are examples of two such tests.
A representative set of conditions, with some associated
comments, Is given in Table 6-1. Figure 6-1 illustrates the
variation of threshold voltage with temperature for state-
of-the-art silicon MOSFETs. Both n- and p-channe!
devices change from enhancement mode to depletion mode
at about 350 °C. Figure 6-2 illustrates the drain
characteristics of a SiC MOSFET at 650 °C. The
61
~ n
0.8
0.6
S o.4
-
0
~ 0.2
co
o
> o
o
it, -0.2
o4
-0.6
-0.8
-1 .o
Is
c
~v
.c
cl 2
e-Channel Devices
_~
- - 1 1 ~1 1 1 1 1 ~I I I I I I
0 50 100 150 200 250 300 350 400
Temperature (°C)
FIGURE 6-1 Variations in threshold voltage for p- and e-type
silicon MOSFETs with temperature. SOURCE: Grzybowski and
Tyson (1993).
T = 923 K
_~
9V
6V
3V
OV
1 1 1 ~
0 5 10 15 20 25
Drain Voltage (V)
FIGURE 6-2 Drain characteristics of a SiC inversion-mode
MOSFET at 650 °C. SOURCE: Palmour et al. (1991).
OCR for page 62
Materials for High-Temperature Semiconductor Devices
TABLE 6-1 Short-Term Constant-Temperature Tests
Temp. Attachment
Device Type (°C) Comments Substrate Method Reference
SiC 25-650, Gain increases BN plate Not reported Palmour et al., 1991
transistors unpacked with temp.
SiC 25-350, Prototypes Not reported Not attached Palmour, 1993
transistors packaged available (wafer probe)
SiC diode 25-550 Very low Not reported Not reported Ghezzo et al., 1992
leakage
currents
SiC pressure 25-400 Piezo-resistive None Not reported Shor et al., 1994
sensors bridge devices
SiC 25-350 (as a Small gain Alumina or Braze Tomana et al., 1993
amplifiers hybrid IC) change with glass ceramic
temp.
Silicon
transistors
-65-450
(both FETs
and bipolar)
Gain decreases Alumina Silver glass
with temp.
Grzybowski, 1991;
Grzybowski and Tyson,
1993
characteristics are normal for MOSFETs, with low
leakage and relatively constant gain.
These results clearly indicate that devices in both
materials systems have been made that operate at
temperatures well above the current limits of fielded
electronic systems, typically about 125° C. The results
are also consistent with the fundamental limits of device
operation, based on the characteristics of each material of
energy gap, effective mass, minority carrier lifetime, and
leakage currents.
CONSTANT-TEMPERATURE L1~E TESTS
Constant-temperature life tests are also encouraging
(Table 6-2), although much work remains to be done in
this area. The times on tests at the temperatures indicated
are too small to be conclusive, however. Effects such as
metal electromigration, impurity diffusion in the
semiconductor, and phase changes occurring in contact
regions, have not yet been adequately tested. A possible
exception is the last result, which was based on silicon
integrated circuits with conventional metallization and
feature sizes that are large (about 7.5 micrometers) by
current standards. This result suggests that silicon-based
62
circuits with conventional metallization may be useful to
temperatures well above the current limit of 125 °C.
THERMAL-CYCLING TESTS
Thermal-cycling tests logically follow after the short-
term and constant-temperature tests. Thermal-cycling tests
are absolutely essential for evaluating suitability of
devices intended for use at elevated temperatures. It is
well known, and is a major limitation in conventional
temperature electronics, that thermal cycling results in
failures that are not discovered by constant-temperature
tests. One class of these failures is associated with the
work-hardening of parts of the device, its metallization,
the package attachment, and the package itself. In flip-
chip technology, for example, the work-hardening of the
solder bumps that are used to hold the device in place and
form the interconnects is a well-known limitation. In fact,
a substantial amount of development has been devoted to
minimizing this problem. For elevated-temperature
electronics, these mechanisms will almost certainly be
more of a limitation, since the temperature swings will be
larger.
OCR for page 63
Device Testing for High-Temperature Electronic Materials
TABLE 6-2 Constant-Temperature Life Tests
Time Temp. Attachment
Device Type (hrs) (°C) Substrate Method
Reference
SiC diode rectifiers1,000 350 Hermetic glass Not reported Edmond et al., 1991
packages
Silicon MOSFETS1,000 200 Alumina AlSi eutectic Palmer and
Heckman, 1978
Silicon bipolar quad500 300 Not reported Not reported Beasom and
op-amp Patterson, 1982
Silicon-based ring4,000 250 Not reported Not reported Migitaka and
oscillators Kurachi, 1994
These limitations may demand new and innovative
techniques for device attachment and connection, such as
the use of graded attachment techniques or compliant
attachment methods, in which the differences in thermal
expansion are taken up by a relatively flexible part of the
attachment. The use of different attachment materials may
also be useful. For example, the use of amalgams has
been explored on a preliminary basis. The use of these
materials would allow one to make the rigid attachment at
a temperature that is intermediate between the extremes,
thus minimizing the stress that occurs at either extreme.
FUTURE REQUIREMENTS FOR HIGH
TEMPERAlllRE TESTING
The testing of devices, circuits, and systems intended
for high-temperature operation is more difficult than
testing for lower-temperature situations. For these lower-
temperature applications, the concepts of step-stress
testing and accelerated aging are established. In these two
approaches, the device under test is subjected to
increasingly higher temperatures and the failure rates
noted. In a well-behaved test, the resulting failure rates
63
will allow the calculation of an activation energy, which
will in turn allow the prediction of failure rates at lower
temperatures.
The situation, however, is less clear for higher-
temperature devices. For example, the mere testing at
higher temperatures is a challenge, with a lack of
equipment available for these higher-temperature tests.
Also, a key assumption for accelerated testing is that the
mechanisms of failure are the same for the accelerated
test as for the application. This assumption has not been
shown to be valid, and may not be true for many tests.
For example, it is likely that the material used to mount
the devices to the substrates would melt in accelerated
testing, thus introducing a new failure mechanism and
invalidating the test.
A possible solution to this problem is the continuous-
variables testing method. This method involves the
measurement of parameters with very high resolution. In
these tests, the device conditions are similar to those of
the intended application. By careful monitoring of the
device parameters, failure mechanisms can be detected at
early stages. Use of this technique eliminates the problems
associated with step-stress and accelerated testing, in
which new failure modes may be introduced.
OCR for page 64
Representative terms from entire chapter:
accelerated testing
