5
Communications, Computers, Displays, and Sensors

The communications, computers, displays, and sensor systems for the dismounted soldier will provide the soldier with information about location and surroundings, evaluate tactical intelligence, assist in targeting, and permit voice and data communications with squad members and field operations centers. These systems will be introduced with modest capabilities in the fully developed Land Warrior equipment and will evolve to higher performance levels to meet increasing demands. Unfortunately, the Land Warrior systems will require a large amount of electric power. Table 5-1 lists estimated power requirements for the communications, computing, display, and sensor functions of the Land Warrior system.

The data in Table 5-1 clearly indicate that most of the energy dissipated in the Land Warrior system will be associated with the radios and computers to be carried by soldiers and, therefore, that the electronics associated with communications and computing functions afford the greatest opportunities for energy savings. The challenge for future Land Warrior systems and successor systems will be to reduce electrical energy consumption while increasing performance to meet projected increases in communications bandwidth, data file sizes, and computational performance.

It is important for the Army to recognize that the electronics industry faces similar challenges in commercial markets and is developing a wide range of low power technologies and design methodologies that are directly applicable to portable military equipment. These emerging technologies will have such a dramatic impact on the energy consumed in performing digital electronic functions—reductions anywhere from a factor of 10 to a factor of 50 are possible—that the Army must either use them or risk fielding equipment that is markedly inferior to commercially available equipment.

Specifically, industry is being driven to increase the performance and simultaneously improve the battery life of commercial products, including portable communications equipment, such as cellular phones and pagers; portable computing devices, such as laptops, palm-tops, and pocket organizers; and portable audio and video equipment, such as camcorders, audio tape and CD



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Energy-Efficient Technologies for the Dismounted Soldier 5 Communications, Computers, Displays, and Sensors The communications, computers, displays, and sensor systems for the dismounted soldier will provide the soldier with information about location and surroundings, evaluate tactical intelligence, assist in targeting, and permit voice and data communications with squad members and field operations centers. These systems will be introduced with modest capabilities in the fully developed Land Warrior equipment and will evolve to higher performance levels to meet increasing demands. Unfortunately, the Land Warrior systems will require a large amount of electric power. Table 5-1 lists estimated power requirements for the communications, computing, display, and sensor functions of the Land Warrior system. The data in Table 5-1 clearly indicate that most of the energy dissipated in the Land Warrior system will be associated with the radios and computers to be carried by soldiers and, therefore, that the electronics associated with communications and computing functions afford the greatest opportunities for energy savings. The challenge for future Land Warrior systems and successor systems will be to reduce electrical energy consumption while increasing performance to meet projected increases in communications bandwidth, data file sizes, and computational performance. It is important for the Army to recognize that the electronics industry faces similar challenges in commercial markets and is developing a wide range of low power technologies and design methodologies that are directly applicable to portable military equipment. These emerging technologies will have such a dramatic impact on the energy consumed in performing digital electronic functions—reductions anywhere from a factor of 10 to a factor of 50 are possible—that the Army must either use them or risk fielding equipment that is markedly inferior to commercially available equipment. Specifically, industry is being driven to increase the performance and simultaneously improve the battery life of commercial products, including portable communications equipment, such as cellular phones and pagers; portable computing devices, such as laptops, palm-tops, and pocket organizers; and portable audio and video equipment, such as camcorders, audio tape and CD

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Energy-Efficient Technologies for the Dismounted Soldier TABLE 5-1 Power Requirements of the Land Warrior System by Function Function Operating Power Communications Soldier radio 7.4 W Squad radio 14.0 W Computer 14.8 W   Displays Hand-held flat panel display 6.4 W   Helmet-mounted display 4.9 W   Integrated sight module display 2.6 W Sensors 7.9 W players, and portable television sets. Low power technologies and design methodologies are being developed in the following general categories: low-voltage semiconductor processing technology power optimizing hardware design methodologies power optimizing software design methodologies   This chapter reviews commercial trends that are driving the development of low power technology. It describes how new low power technologies and design methodologies are being used to design commercial products, details the magnitude of improvements in performance, and projects improvements that may be possible in the future. Subsequent sections contain detailed studies of the communications, computing, sensors, and display equipment to be used by Land Warrior, along with descriptions and assessments of enabling technologies. TRENDS IN DESIGNING COMMERCIAL PORTABLE EQUIPMENT Suppliers of portable consumer electronics face conflicting demands of increasing performance while decreasing power drain1 in order to provide longer battery life. Two of the best examples are cellular telephones and laptop computers. Figure 5-1 plots the complexity of high performance microprocessors by the year each device was introduced. The graph shows that microcomputer complexity has increased by a factor of ten every seven years, following Moore's 1   Power is a rate of change, so the term "power drain" is technically imprecise. The term is never the less widely used in industry to describe the power performance of microprocessing devices as measured in mW per MIPS.

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Energy-Efficient Technologies for the Dismounted Soldier Law of integrated circuit complexity (see Chapter 4). Figure 5-2 plots the complexity of radio pagers and cellular phones by year of introduction. Predictably, it shows that the complexity of these products is driven by the complexity of integrated circuits; these slopes also follow Moore's Law. A frequently unrecognized implication of the data in Figures 5-1 and 5-2 is that, because power drain tends to track complexity, the power requirements of semiconductor products have also increased exponentially. The thousand fold increase in complexity over the past 25 years has driven circuit complexity to the point that power drain has become a major problem facing the electronics industry. The power dissipation of a digital logic integrated circuit is determined by several factors, including the operating voltage of the circuit, the complexity of FIGURE 5-1 Complexity of microprocessors by year of introduction.

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Energy-Efficient Technologies for the Dismounted Soldier Notes SSI = small scale integration LSI = large scale integration VLSI = very large scale integration FIGURE 5-2 Complexity of cellular phones and pagers by year of introduction. the circuit, the operating frequency of the elements of the circuit, and the speed-power product of the process used to fabricate the circuit. For a circuit in which all of the logic elements operate at the same frequency, the relation of these parameters can be expressed as: Pd ~Kp·C·F·SP (1) Pd = power dissipation of the circuit. Kp = a process and supply voltage dependent constant. C = the complexity of the circuit in equivalent gates. F = the operating frequency of the circuit. SP = the speed-power product of the semiconductor process. Thus, two major factors besides complexity influence power drain: the operating frequency of the logic and the speed-power characteristics of the semiconductor process.

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-3 Operating frequency of high-end microprocessors used in desk-top computers by year of introduction. Figure 5-3 plots the operating frequency of the high-end microprocessors used in desktop computers. Performance, measured by maximum operating frequency, has increased steadily, by a factor of ten every nine years. The performance of other digital logic functions, such as digital signal processors and numeric coprocessors, has followed a similar trend. This performance trend is well known and has been one of the main reasons for the success of the personal computer and workstation industries, as well as most consumer electronics products. The frequently unrecognized implication of this trend has been an exponential increase in the inherent energy consumption of very-large-scale integrated (VLSI) circuits. Taken together, the data in Figures 5-1 and 5-3 indicate that two of the factors in Equation (1), complexity (C) and frequency (F), have been increasing at a combined exponential rate of a factor of 100 every eight years. Figure 5-4 plots the speed-power efficiency of several bipolar and CMOS (complementary metal-oxide semiconductor) integrated circuit processes by the year they were first used for commercial production. Speed-power efficiency has improved by a factor of ten every eight years. Although this improvement closely tracks the increase in complexity of VLSI chips, it does not compensate for the combined rate of increase in complexity and performance. Indeed, the net combined rate of change in the three parameters in Equation (1) is a tenfold increase every eight years. The semiconductor industry has been rapidly approaching a situation in which power will become a major barrier to further improvements in complexity and performance. The problems include: poor battery life for portable equipment;

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-4 Improvement in the speed-power characteristic of integrated circuit processes by year of introduction. heat dissipation and cooling problems for high-performance chips and systems; and reliability problems associated with elevated operating temperatures of semiconductors. Until recently, the electronics industry has not paid much attention to power drain and its associated problems. This situation is highlighted in Figure 5-5, which shows the power drain per million instructions per second (MIPS) of the leading commercial microprocessors through the year 1993. The chart shows that there was essentially no reduction in the power drain of these products through 1993. The power efficiency on a mW/MIPS basis actually degraded over time. In fact, the first samples of the Pentium™ processor reportedly overheated because they exceeded the dissipation limit of their packages! The products shown in Figure 5-5 are high-end microprocessors designed for desk-top applications, for which power drain was not considered an important design parameter. The only power consideration was that the devices should not exceed the heat dissipation of the planned packaging. In the early 1990s, however, cellular telephones, personal digital assistants, laptop computers, camcorders, and other portable products began to sell in significant numbers. Battery life became

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-5 Power drain versus performance for microprocessors used in desk top computers from 1989 to 1993. an important design issue for these products, and new microprocessor designs aimed at optimizing performance per unit of power drain appeared on the market. The improvement in the performance of several products is shown in Figure 5-6. Here, products such as the ARM™ central processor unit (CPU) from Advanced RISC (reduced instruction set computer) Machines and the Hobbit™ from AT&T, showed significantly better performance per unit of power (by a factor of 25 in the case of the ARM processor). Subsequent products from NEC and Hitachi, together with process improvements and design changes that allowed low-voltage operation, have pushed the power per MIPS figure down to 1 mW. One of the most startling aspects of the data in Figure 5-6 is that the power required by microprocessors designed for portable, battery-operated devices is decreasing at the astounding rate of a factor of ten in two-and-one-half years. To show that this is not an isolated case, Figure 5-7 plots the same performance for communications-oriented DSPs and shows that they are being improved at the same rate. The recent improvements in microprocessors and general-purpose programmable DSPs are being driven by a number of design and implementation changes: First and foremost, power drain is being treated as a key design parameter. Architectures are being optimized for each application. In the case of microprocessors, small, power efficient RISC CPUs are being developed and used for portable applications over the larger complete instruction set computer (CISC) architectures, such as the Pentium™, that are used in desk-top computers. For example, the ARM™ RISC CPU contains 35,000 transistors, compared with 187,000 in the PowerPC™.

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-6 Power drain characteristics of recent microprocessors. FIGURE 5-7 Performance of general-purpose programmable DSP by year of introduction.

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Energy-Efficient Technologies for the Dismounted Soldier Low power design techniques are being developed and used with the same priority previously given to maximizing speed and other performance parameters. Examples of these techniques include removing clock signals from unused functions, selecting devices that are sized to optimize speed and power, and selecting the lowest function operating speeds necessary to complete tasks. Operating voltage is being lowered to the lowest practical value. Of all the system parameters affecting power drain, changes in operating voltage have the greatest impact. As illustrated in Figure 5-8, the power drain of the basic complementary logic gate structure is proportional to the square of the system operating voltage. This relationship yields the normalized power drain versus operating voltage slope shown in Figure 5-9, which indicates that a 30-fold reduction in logic power could ideally be achieved by lowering the supply voltage from 5.0 V to 0.9 V. In practice, it is difficult to implement high-performance logic functions that operate at 1 V today, but substantial power drain reductions have been achieved by moving from 5.0 V to 3.3 V for portable computer systems and cellular phones (a factor of 2.3) and to 2.0 V for consumer audio products (a factor of 6.25). These voltage changes have been achieved by using fairly straightforward modifications of the basic CMOS fabrication processes used in the early 1990s. However, industry is working toward advanced low-voltage FIGURE 5-8 Basic complementary gate structure.

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-9 Power savings of low-voltage logic operation. semiconductor processes that can implement high-speed logic at even lower voltages, and microprocessors and DSPs that provide more than 250 MIPS at 1.5 V should be commercially available by the year 2000. Manufacturers of portable equipment, at the product level, are using many of the techniques used by component-level designers, as well as several system-oriented methodologies that significantly reduce power drain. These techniques include: System supply voltages are being lowered, and the operating voltage of major subsystems is being selected to optimize both the energy efficiency and the performance of the element. DC-DC converters (Chandrakasan et al., 1994) are often used to provide different supply voltages for key subsystems as shown in Figure 5-10. In camcorders and cellular phones, for example, a ''high" voltage battery (typically 6 V) directly supplies analog functions, such as RF power amplifiers or auto-focusing motors that operate best at 5 V, while high-efficiency DC-DC converters are used to supply 2 or 3 V to digital elements. The overall effect is a significant reduction in power drain compared with schemes that operate all functions at the same supply voltage or use loss regulators to generate the lower voltages. System architectures are being developed to lower power drain. Examples of this approach include: function-level designs that use parallel logic elements to reduce the operating frequency of each element and the total power drain of the function while maintaining overall performance; and, system and function designs based on new algorithms that reduce power drain. The implications of implementing functions in hardware versus software are being studied carefully, and many functions that have been software-based are being implemented in hardware to reduce power drain. One example of this is the 50-fold reduction in power achieved when the trellis decoding function used in cellular telephones was switched from software to hardware.  

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-10 Power distribution used in portable products. Commercial portable product designs are quickly adopting ASIC (application-specific integrated circuit) and system-on-a-chip design methodologies (explained in Chapter 4). These methodologies make many of the techniques described above practical by providing the means for implementing them. The reduction of supply voltages is facilitated, for example, because in the ASIC environment elements can be designed to operate at optimal voltages; the same low-voltage performance may not be duplicated using commercial components.   The single chip environment readily accommodates the implementation of architectural level changes with the greatest potential impact on power drain. The single chip environment eliminates the large interconnect capacitances associated with multichip systems. In high speed systems, driving signals across interchip connection paths requires significant power; in many computer systems this accounts for most of the system power. This point is highlighted in Figure 5-11, which plots the power drain associated with single-line and eight-bit bus

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Energy-Efficient Technologies for the Dismounted Soldier Unlike the widely used charge coupled device (CCD) imagers, APS sensors do not require repetitive charge transfers and therefore do not require special fabrication technology. APS, as developed at the Jet Propulsion Laboratory (of the National Aeronautics and Space Administration), is fabricated by commercially available CMOS technology, enabling implementation of highly integrated "camera-on-a-chip" imaging systems (Dickinson et al., 1995; Nixon et al., 1996) Unlike CCD, a CMOS APS is a random access, low capacitance device. Furthermore, use of CMOS technology allows integration of on-chip timing and controls with the APS. The resultant imager system-on-a-chip exhibits ultra-low power requirements (more than a 100-fold reduction compared to the state of the art) and extensive miniaturization (more than tenfold reductions in mass and size). Integration of on-chip electronics for camera timing and control, signal conditioning and noise shaping, analog-to-digital conversion, and interface definition leads to imaging systems with extremely high performance (low noise, high functionality, high speed, high reliability, and ultra-low power requirements.) A CMOS APS operates from a single 5 V (or 3.3 V) supply and features large format (1024×1024), high resolution (< 12 µm pitch), wide dynamic range (more than 75 dB), digital I/O, random access readout, low smear, antiblooming control, and electronic shuttering, with excellent imaging performance (quantum efficiency similar to interline CCD, and noise < 12 e- r.m.s.). It enables visible imaging in many different formats. The total system power requirement is far lower than the requirement of the analog-to-digital converter alone in a conventional imaging system because there is no need to drive the analog signal off the chip before the converter. Because APS arrays are completely silicon-based, including the detectors, they respond in the visible and near-infrared (0.4 µm to 1.0 µm) wavelengths and fall outside the wavelength bands of key interest to the Army. Nevertheless, the lessons of this commercial technology have led to lower power consumption and lower costs in interface electronics, which can be translated to improvements in similar interfaces on infrared detector arrays. The challenge will be to find ways to achieve single-chip integration of the detector materials that can sense the longer wavelength radiation bands (3 µm to 5 µm; and 8 µm to 12 µm) by developing thin-film deposition techniques for both BST and vanadium oxide, the materials used for uncooled detectors. Indeed, a long wavelength vanadium oxide microbolometer focal plane array based on commercial CMOS technology is available for both commercial and military use (Butler et al., 1996). The developers have integrated onto a single focal plane array features such as nonuniformity correction, auto gain and level correction, television video, and analog-to-digital converter output. The array is a 327×245 pixel array with a 10-bit analog-to-digital converter at a 6.1 MHz output data rate and a 60 Hz frame rate. It requires less than 500 mW of power, 250 mW of which is attributed to the analog-to-digital converter. Much of the energy savings in this display comes from standardizing to 5 V with commercial

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Energy-Efficient Technologies for the Dismounted Soldier CMOS and using an on-chip analog-to-digital converter. These numbers will improve with the push towards lower chip voltages. Research and Development Future R&D should focus on further reducing dependence on the TEC. In addition to ongoing work to improve the yield of capacitive and resistive bolometers, thermocouple bolometers for reducing the thermal offset energy consumption at the TEC should be investigated. Once MEMS fabrication techniques have advanced, microbolometer structures could be integrated onto chips with CMOS circuits without degrading CMOS performance. Ultimately, merging MEMS and CMOS should bring down the cost of these sensor systems. A commercial industry guideline similar to the NTRS should improve technology development. Laser Detectors Currently, a single laser detector mounted in a frontal position on the helmet is used for Land Warrior. This positioning does not optimize situational awareness because when lasers come into play on the battlefield, they will be used largely as a means of acquiring targets, whether tanks, trucks, or foot soldiers. Laser detection would be enhanced with sensor coverage in all four directions of the helmet and a sensor net on the soldier's vest. This would improve the soldier's chances of being forewarned when he or she has been targeted. Cloaking the soldier in a large number of surface-mounted detectors at various points on the vest and helmet, however, would be costly in terms of energy; the duty cycle for the laser detector will probably be 50 percent or more over the course of a mission. Furthermore, it is difficult to make sensors rugged enough to prevent damage in the combat environment. One way to solve this problem would be to weave 100 or more lensed light collectors in the form of multimode fibers into the vest and helmet. By fusing the output ends of the fibers, their integrated output could be used to illuminate a common detector. Two common detectors, one located in the helmet and one in the vest, are illustrated in Figure 5-18. The embedded collectors could capture laser radiation from different locations and directions and feed it to a combination detector-amplifier. A network of optical collectors might also double as the backbone for an infrared wireless link between the helmet, vest, and weapon to handle data. Power requirements for the wireless communications interfaces needed to link the soldier subsystems are discussed in a later section in this chapter. The heart of the laser detector technology is similar to the technology of infrared imaging arrays, i.e., a single detector with an adjacent preamplifier and ASIC (application-specific integrated circuit). One might locate three or four

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Energy-Efficient Technologies for the Dismounted Soldier FIGURE 5-18 Soldier's vest and helmet with laser detectors. detector-amplifier combinations on the same chip, each fed from a fiber bundle that recovers signals from a different direction (enabling the user to distinguish the general direction of the source). Other functions might be included on the chip to permit the user to measure wavelength and other signature information, such as pulse length. If the large infrared sensor arrays and their associated control and analog-to-digital converter electronics can be deployed requiring 50 mW of power using 5 V CMOS technology, the same technology applied to a single system would enable power requirements of less than 5 mW.

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Energy-Efficient Technologies for the Dismounted Soldier Research and Development Weaving multimode fibers to serve as light collectors into the soldier's Kevlar vest and helmet material will require supporting technology development. Laser Rangefinders and Infrared Pointer Technology The minimum average optical output of the laser rangefinder is 1 mJ. This level is currently achieved with a diode-pumped solid state neodymium: yttrium lithium fluoride (Nd:YLF) laser with difference frequency shifted to an eye-safe wavelength of 1.5 mm. The rangefinder has a nominal operating power of 50 mW and peak power requirements of 750 mW in the Q-switching mode. Because the range to a target can usually be established with a single pulse, the duty cycle during peak power mode of operation is expected to be very low (< 3 × 10-5 percent). Consequently, energy consumption is dominated by the nominal operating condition. For the 50 mW quoted, the 5 percent duty cycle implies that the average power requirement over a 12-hour mission will be 2.5 mW. In contrast, the infrared pointer is a light emitting diode operated in continuous-wave mode and has an output power of 1 mW. Its peak power requirement is 75 mW, and its 5 percent duty cycle implies that the average power required over a mission will be about 4 mW. Laser Rangefinder With diode lasers, it is possible to achieve 65 percent power conversion efficiencies from edge-emitting lasers, although 25 percent is typical of commercial lasers. Under the best of circumstances, one might also obtain 80 percent power conversion efficiencies in pumping the Nd:YLF laser with the diode laser and another 71 percent when converting from 1.06 µm to 1.5 µm. Naturally, the actual wavelength conversion efficiencies are considerably worse than this, so that most of the power requirement in the laser rangefinder is accounted for by converting the optical energy to the 1.5 µm wavelength. This rather complicated process for obtaining the 1.5 µm was used in the early stages of the Land Warrior because there were no direct diode sources of 1.5 µm that could supply energy pulses as large as 1 mJ. However, if the current trends in diode laser technology development continue, a 1.5 µm wavelength diode laser could be switched to achieve the 1 mJ per pulse requirement. Because p-n diode technology is one of the most efficient means of converting from electrical to optical energy, a direct diode replacement for the current arrangement would optimize the design in terms of power consumption. Given the current trends, an adequate R&D strategy would be to track this particular technology and convert to a direct diode laser source when it becomes available.

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Energy-Efficient Technologies for the Dismounted Soldier Infrared Pointer For the infrared pointer, although the power requirement is dominated by the electrical-to-optical conversion efficiency, 10 mW of the total 75 mW of operating power is nonetheless attributable to the electronics interface with the computer. By using ultra-low power design strategies, the power required at this interface can be reduced below 1 mW. With respect to the electrical-to-optical conversion, the typical power conversion efficiencies of light emitting diodes (LED) are similar to diode lasers, but because of the radiation pattern, only a small percentage of the emitted light is subtended by the collection optics (6 percent with an optimized design for the collection optics). Thus, the optical conversion efficiency could be further improved by replacing the diode laser with an LED, which would reduce the power required to generate 1 mW of infrared radiation to approximately 4 mW and would result in a net total drive power of 5 mW for the infrared pointer. Cost has been the major reason for selecting an LED over a laser diode in many applications, but costs are expected to fall as multimedia communications using high bandwidth fiber optics reach the mass consumer market. Research and Development High optical losses in the current prototypes will be offset to some degree by expected low duty cycles. Low average power requirements make R&D to reduce energy loss in the infrared pointers a low priority compared to losses due to other sensors. The optical conversion efficiencies are expected to continue to rise as a result of heavy investment in R&D by telecommunications companies and other companies concerned with users of multimedia and the internet. Commercial R&D will focus heavily on lowering the cost of the optical subcomponents. The Army stands to benefit from this commercial investment, although commercial interests will not be concerned with packaging these devices compactly to withstand the rugged environment of military operations. Global Positioning System The most common use of the GPS (global positioning system) by the dismounted soldier is for land navigation. GPS is also used in search and rescue operations, and there are plans to adopt it for precision delivery of cargo by parachute or paraglider. A major concern to the Army is the potential for primary interference from deliberate jamming or spoofing by an adversary or by friendly forces. Therefore, all GPS-based navigation systems must have one of the following features: sufficient jamming-to-signal ratio strength to navigate through the jamming environment; the ability to null out the jamming signal; or an alternative to GPS for navigating through the jamming environment. Full GPS

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Energy-Efficient Technologies for the Dismounted Soldier accuracy would thus be denied to the enemy by selective availability and by antispoofing security procedures. The GPS receiver in the soldier's sensor suite must be capable of meeting all of these requirements. The GPS receiver in the Land Warrior ensemble has two power management modes, continuous mode and fixed mode. In the continuous mode, the receiver is in continuous operation, and the battery is good for about 10 hours. In fixed mode, the unit is powered on once every 15 minutes, increasing the battery life to about 40 hours. Another power management option would be to activate the GPS only on demand because the average mobility of a foot soldier does not require continuous updates. The Army is also investing in a longer term program to develop an ULPE GPS module. Currently, GPS research is focused on three topics: integrated CMOS technology; low voltage front-end receiver circuits; and fast synchronization and reacquisition algorithms. The operation of a GPS receiver involves three data acquisition phases: acquisition of the almanac information; acquisition of the ephemera information; and acquisition of phase synchronization. The almanac data takes at least 12.5 minutes to acquire and must be updated every few days. Ephemera information takes about one minute to acquire and must be updated about every four hours. Even though these two kinds of data take a long time to acquire—the low data rate of 50 bits per second still results in a duty cycle of less than one percent—the impact on energy consumption is not as important as the problem of phase synchronization. Therefore, attempts to reduce the power requirement for GPS have been focused on reducing the active power and the time required in phase synchronization (Meng, 1997). To reduce the active power of a GPS receiver, the design of both analog and digital circuits must be optimized for low power. With recent developments in CMOS technology, highly integrated circuits can operate in the GHz range, which provides a low cost, low power solution to the problem. Based on a 0.35 µm CMOS design, a combined low noise amplifier and mixer operating at 1.6 GHz requires less than 7.5 mW with reasonable gain of 20 dB and less than 3 dB of noise figure (Shahani et al., 1997). The GPS front-end circuits can be implemented in less than 10 mW, using standard CMOS technology (Meng, 1997). After the GPS signal has been converted to a low intermediate frequency on the order of a few megahertz (MHz) in the receiver, an analog-to-digital converter can be used to digitize the analog data to binary bits. A 2-bit converter operating at 20 Mhz requires less than 1 mW of power, which does not impose a power concern on the overall design (Meng, 1997). A composite correlator architecture has been developed for GPS data acquisition to implement multiple-channel demodulation without incurring much overhead in power. As a result, the GPS receiver can perform 6-channel or 12-channel acquisition at a fairly low clock rate without the usual power penalty. The active power for data acquisition is estimated to be around 10 mW, assuming continuous operation (Meng, 1997).

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Energy-Efficient Technologies for the Dismounted Soldier The base-band signal processing for the calculation of positions and timing will employ dedicated low power digital circuits operating at 1 V supply voltage. Using dedicated hardware, flexibility is traded off for a reduction in power. Simulation shows that the power required for calculating positions and timing is negligible (less than 1 mW) because updated information is only needed once every few seconds (Meng, 1997). Current GPS systems take at least 1 second to reacquire phase synchronization, to demodulate the received signal accurately, and to estimate the pseudo-range. Instead of using the standard early-delay loop for this purpose, a phase-error interpolation scheme was developed that requires only a fraction of a second for accurate phase synchronization. By employing this new phase-lock algorithm, the overall average power, or the duty cycle, is reduced. For example, to monitor a position continuously, the GPS may have to be turned on every 2 seconds without losing bit synchronization. If it takes only 100 milliseconds, instead of 1 second, for phase synchronization, the total energy dissipation will be reduced by a factor of 10, regardless of the actual active power (Meng, 1997). A single-chip GPS receiver fabricated in the standard 0.35 CMOS technology that requires less than 20 mW of active power is now feasible. When factoring in the duty cycle, a GPS receiver estimating a position every 2 seconds will require an average power of 1 mW, which allows a much longer battery life than any of the current designs (Meng, 1997). Table 5-11 shows the Army's progress in reducing the power requirement of GPS receivers. Research and Development According to projections by Booz-Allen Hamilton, Inc., there are five major commercial arenas that can be expected to drive the GPS technology base between 1994 and 2003 (NRC, 1995): land vehicles (223 million units fielded) marine vessels (21 million units fielded) aircraft (312,000 units fielded) surveying/mapping (690,000 units fielded) personal use   GPS market forces are dominated by land vehicles, marine vessels, surveying and mapping, and aircraft. Personal use, including self-surveys, golfing, emergency location, fishing, sailing, and hiking, is expected to be negligible. However, products for personal use are expected to have the same low power consumption and portability characteristics that are needed for the military. The only other commercial market that might potentially need low power would be surveying and mapping. Neither market is large enough to stimulate a major commercial technology push toward Army goals; therefore, low power GPS for

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Energy-Efficient Technologies for the Dismounted Soldier TABLE 5-11 GPS Power Requirements Nomenclature Year Battery Power (W) AN/PSN-8 1985 BA 5590/U 46.5 AN/PSN-9 1987 BA 6598/U 9.8 AN/PSN-10 1988 BA 5800/U 2 each BA 3058/U 8 each 5.0 AN/PSN-11 1993 BA 5800/U 2 each BA 3058/U 8 each 5.0 Land Warrior 2000 — 1.5 the dismounted soldier and other military applications will require R&D investment by the Army. Wireless Communication Interfaces Communications among the weapon, vest, and helmet in the objective Land Warrior system will be accomplished with two RS-232 cable data links connecting the vest computer with the ISM. The ISM can support two displays. One is an actual display in the eyepiece on the ISM located on the weapon. The other is a video output, RS170/RS422, from the ISM either to the vest computer or directly to a display in the IHAS. Normally the ISM feeds the computer, which feeds the IHAS. Replacing the cables with a wireless interface would have advantages of lower weight and more flexibility. Adopting a wireless interface, however, means using separate batteries for each of the three sensor suite subsystems in the vest, the weapon, and the helmet. Of the three subsystems, the helmet will require the smallest, lightest battery in order to minimize torque on the head from the weight of sensor electronics. This also means that the size and shape of the electronics package must be ergonomically sound. The vest-mounted electronics, because they hang directly from the torso close to the body's center of gravity, have the fewest restrictions on size and weight. Current and Future Technology There are two possible approaches to using wireless connectors. One is to rely on radio frequency transmission between the three separate subsystems. The other is to develop infrared frequency transmission (using either LEDs or diode lasers) that use fiber collector nets to complete the link through a variety of different orientations of the subsystems with respect to each other. The latter

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Energy-Efficient Technologies for the Dismounted Soldier approach could take advantage of the light collection technology developed to enhance the laser detector (described earlier). Radio Frequency Wireless Interface The Land Warrior system uses an RS-232 bus for a hard-wire interface. In the RS-232 protocols, all nodes are in a continuous listen/transmit mode, whether data is being transmitted or not. An alternative, more energy-efficient protocol would help to reduce the load on the battery. For example, a DARPA supported program for a wireless interface called a BodyLAN (local area network) uses a time division multiple access (TDMA) protocol at a 900 MHz carrier frequency to reduce power. Other features of the BodyLAN are as follows: wireless nodes that can be clipped anywhere on the body reliable network range of 1.5 meter, i.e., limited to the immediate proximity of the body TDMA timing structure with nodes powered on to receive control information and/or data nodes that are provided regular transmission opportunities by the controlling hub and otherwise power-down the transmitters varying levels of communications reliability layered on top of the basic structure, ranging from unchecked datagrams to a highly reliable forward-error-correction scheme coupled with packet retries   The anticipated performance characteristics of a BodyLAN system following this set of protocol rules are shown in Table 5-12. Optical Wireless Interface Once optical wireless links are available at comparable energy consumption levels to those achievable with BodyLAN, one can begin to trade off the advantages of optical and radio frequency links. The chief reason for considering optical interfaces is that they are intrinsically wideband and can thus easily accommodate a more complex sensor suite. Optical links are also highly resistant to jamming. Trade-offs between low signature, reliability, ease of maintenance, and other criteria, will have to be carefully considered when weighing the merits of designs employing these two wireless technologies, but it will not be necessary to choose one or the other. Optimal performance can probably be achieved by including both a radio frequency and an optical wireless link in the sensor suite. This dual-string design would permit operation in either a normal mode or a clandestine antijam mode, as needed. The power requirement for a wireless configuration will never be as good as what can be achieved with a well designed hard-wire link. Still, a wireless link should be more reliable because hard-wire connector joints are subject to severe stress in the field.

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Energy-Efficient Technologies for the Dismounted Soldier TABLE 5-12 Performance Characteristics of the BodyLAN Specification Near Term Future Size = 1.6 in3 = 0.56 in3 Weight = 15 g = 5 g Aggregate raw data rate 70 kbps 70 kbps Power required (full rate) 7.6 mW 5 mW Power required (sleep) 1.3 mW 0.03 mW Peak transmit power 375 µm 375 µm Number of nodes 128 128 FINDINGS Advancing microelectronics technologies hold great promise for reducing the power requirements of systems for the dismounted soldier. Processing capability and device complexity are growing according to Moore's law, i.e., doubling every 18 months. Processor clock frequency has also risen at a rate of about a factor of ten every nine years. These improvements have brought into focus the importance of energy considerations, especially for portable devices. The performance of portable devices is subject to the limitations of battery technology, which is improving comparatively slowly, despite many years of generous spending on R&D. Both the Army and commercial industry are seeking more energy-efficient systems. Fortunately, they are achievable in most of the relevant technologies. Communications The energy efficiency of radio frequency wireless transmission is not likely to improve substantially in the future. However, network architectures and communications protocols can be optimized for energy efficiency. Careful attention to circuit design and operation, system architecture, and system integration have reduced the power requirements of some specialized commercial microprocessors (such as those in cellular telephones) by about an order of magnitude in the past few years. Continued improvement can be expected. The energy needed to support transmission of high speed data will increase in relation to other Land Warrior energy demands. A tenet of communications systems for the dismounted soldier should be to deploy the computational components of the system in a manner that minimizes wireless communication. In general, computational components should be placed so that data collection and reduction are performed as close as possible to the site of the data collector.

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Energy-Efficient Technologies for the Dismounted Soldier Computing The Land Warrior computer, basically a general-purpose laptop PC, is connected to all subsystems and is expected to consume about 180 Wh for a 12-hour mission. This demand could be reduced by 50 to 80 percent through system-level power management techniques using general-purpose components and energy-efficient software (compilers that explicitly consider energy per operation). Replacing the general-purpose computer with distributed dedicated processors optimized for low energy consumption could yield reductions of two orders of magnitude. Critical chips within a multimedia terminal combining both computing and radio functions have already been designed to draw 5 mW—three orders of magnitude less than existing commercial counterparts. Displays and Sensors Improvements in the drive electronics for both displays and imaging sensors will account for most of the reductions in power requirements for the sensors, the ISM, the IHAS, and the hand-held displays. Digital control electronics of the sensors can be expected to follow the same trends as other computing devices through the use of lower voltage CMOS technology. The exceptions that will not benefit from this steep falloff are the analog subassemblies in the sensor system (i.e., displays, temperature controllers, pulsed lasers, infrared pointers, etc.). R&D already under way can be expected to reduce the power requirements of the combined display and sensor suite to less than 390 mW, more than an order of magnitude better than estimates in the Land Warrior system design.