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Appendix A
Semiconductor Device Technologies
The integrated circuit (IC) is the underlying component technol-
ogy on which all the devices discussed in this appendix are and wiD
be built in the foreseeable future. For the most part, over the next
five to ten years, ICs win be made from silicon (Si). However, for
special applications requiring radiation hardness and temperature
tolerance, gallium arsenide (GaAs) devices will offer some advan-
tages over silicon. From a production standpoint, GaAs costs will
make these devices a high-end, Tow-volume item until such time as
production costs match those of silicon.
The dominant circuit technologies for the 1990s are expected to
be the complementary metal oxide semiconductor (CMOS), bipolar
emitter coupled logic (ECL), bipolar CMOS (BICMOS), and GaAs,
in that order. Key parameters include feature (gate) density, power
consumption, voltage requirements, and switching current and speed.
The three dominant circuit technologies vary widely with respect
to these parameters. CMOS offers high gate density, low power,
and high switching speeds; bipolar offers high speed, relatively low
density, and high-power consumption; and GaAs offers very high
speeds and Tow power.
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
CMOS will play a dominant role in dynamic memories and other
Tow-cost, lower performance applications. It will continue to be the
245
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246
APPENrDIX A
basic technology of choice for many general-purpose computer sys-
tems. CMOS offers both high speeds and low-power consumption at
high densities. One-micron feature sizes are current state of the art
and subm~cron CMOS is likely in the near term.1
CMOS power dissipation is low enough that some high-perfor-
mance computer systems can be expected to be made of CMOS
(because they can be air-cooled) in the intermediate term. This
assumption, however, win not necessarily be valid forever, because
at higher frequencies CMOS power dissipation may be too high at
room temperature. In addition, cooling below room temperature will
improve the speed of CMOS devices. For example, Control Data Cor-
poration's ETA Systems uses a chilled CMOS in its supercomputer
to enhance system performance.
The geometries of very large scale integrated (V£SI) circuits wiD
continue to shrink, bringing CMOS down to submicron feature sizes.
This shrinkage will result in denser logic and greater capacities for
random access memories (RAM), as wed as decreases in gate delays
and propagation paths leading to improvements in speed.
As the geometries get smaller, ECL's performance advantage
over CMOS lessens for Tow-capacitance circuits. For submicron gate
lengths, CMOS will compete with ECI. in performance for low-
capacitance applications.2
SILICON BIPOLAR EMITTER COUPLED LOGIC
Bipolar emitter coupled logic continues to provide high speeds for
custom logic, gate arrays, and static RAM. The current generations
of higher performance computers (IBM 3090, Crays, Sperry 1100/90,
and NEC's SX-2), minisupercomputers (Convex C-2), and m~nicom-
puters (VAX 8600/~800) use ECL-based technology. In contrast to
CMOS, bipolar devices offer higher speeds with higher power con-
sumption. High-performance computer systems that utilize bipolar
devices require advanced cooling systems (chilled water, immersion
cooling, or Freon cooling) to dissipate heat generated by these de-
vices. For memory, bipolar ECL offers a speed advantage ranging
1CMOS technology offers advantages over ECL for very large scale integrated
(VLSI) circuits with high gate counts and low power. However, it has some disad-
vantages in signal fidelity, impedance mismatch, noise sensitivity, and settling times.
This assumes subnanosecond gate delays for minimum feature size gates with den-
sities greater than 50 K gates per die. Intel's 80386 is a CMOS device with about
300 K devices per die.
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APPENDIX A
247
between a factor of 3 and a factor of 5 over CMOS. For gate arrays,
bipolar devices offer speed advantages ranging between a factor of 2
and a factor of 10 over CMOS, depending on the application.
A significant trend in bipolar technology has been the devel-
opment of methodologies that trade off power and speed so that
designers can use a much larger number of gates in a bipolar {C (as-
suming that most transistors are low power). This innovation greatly
enhances the feasibility of bipolar VESI. Better computer-aided de-
sign (CAD) tools that choose transistor drive capability intelligently
will be required to make the most of this technology.
BIPOLAR COMPLEMENTARY METAL OXIDE
SEMICONDUCTOR
The bipolar complementary metal oxide semiconductor is an
emerging technology that combines the advantages of CMOS and
bipolar approaches. BICMOS technology is likely to be applied in
static RAMs (SRAM), dynamic RAMs (DRAM), and microproces-
sors. It is likely to become a dominant technology for SRAM and a
major technology for application-specific integrated circuits (ASICs).
BICMOS is heavily dependent on CAD tools and process stan-
dardization, which does not exist. Suitable CAD tools and a standard
process for BICMOS will be developed to support the commercial
use of this technology by the mid-1990s.
GALLIUM ARSENIDE
Gallium arsenide's higher electron mobility gives it an inherent
speed advantage over silicon. GaAs devices are being introduced into
the market; small-scale digital circuits and GaAs ICs are produced
in increasingly higher volumes. The speeds of GaAs prototype ICs
surpass those of Si bipolar at Tower power dissipation, so their use
in special computer systems is likely to emerge. In addition, GaAs-
based short- and long-wavelength lasers and light-emitting diodes
have been on the market for several years. Developments in these
technologies, while initially applicable to telecommunications, may
also emerge in third-level interconnect and networking of computers.
Several GaAs devices are in advanced research or development.
GaAs field effect transistors are the most mature of the GaAs tech-
nologies that relate specifically to computing systems and are avail-
able as commercial products. For example, SRAM ranging from 1 K
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248
APPENDIX A
TABLE A.1 Performance of High-Speed Gate Arrays
Number
Technology of Gates
and Company (k)
Power Gate Delay
(mW/gate) (pa) Comments
ECL
NEC 5 1.00 500 Loaded, 1.5,um
NTT 2.5 2.60 78 R.O., 0.5,um
Siemens 9 7.50 150 4 x 4 multiplier
CMOS/SOS 8 0.45 870 Loaded
G aAs
Oki 1 0.27 390 1 sum
Toshiba 2 0.50 215
Tektronix 1.2 0.25 200
SOURCE: Reprinted, with permission, from Greiling (1987~. Copyright
1987 by IEEE.
to 16 K are in production and available from vendors in Japan and
the United States.
Application areas today are almost strictly in complex, digi-
tal signal processing (using SRAMs, read-only memories (ROMs),
high-density logic arrays, and FFT processors) for frequency coun-
ters, correlators, multiplexers and demultiplexers, analog and digital
converters, and time-interval counters that have on-chip clock fre-
quencies above 1 GHz.
Future near-term applications are likely to be in advanced digital
signal processors and telecommunications systems. Systems requir-
ing clock frequencies in the 250-MHz to 3-GHz range and integration
levels of 100 gates per chip will use GaAs ICs.
Mid-term (five years and beyond) applications are likely to be
in high-performance computing systems. Cray, for example, plans
to use GaAs technology (developed in conjunction with Philips) in
the Cray-3 supercomputer, scheduled for delivery in 1991. Fujitsu
is reported to have chosen GaAs/GaAlAs high electron mobility
transistor (HEMT) technology for its next supercomputer.
Tables A.1 and A.2 compare performance of commercially avail-
able silicon CMOS, bipolar, and GaAs devices in gate arrays and
memories.
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APPENDIX A
TABLE A.2 Performance of High-Speed Memories
Technology Size Access Power
and Company (kbits) Time (ne) (mW/1°K) Comments
ECL
Fujitsu 4
NEC
NTT
3.20
2.30
0.85
1.10
Hitachi 4 2.50
Fairchild 64 15.00
NMOS/CMOS
Bell
NMOS
Toshiba
G aAs
Fujitsu 1 1.S0
4 S.00
NTT 4 2.80
16 4.10
6.00
2.40
3.40
4
4
4
64
5.00
17.00
NEC 1
Fujitsu 1
(HEMT)
750
400
950
980
250
14
100
4.7
BOO 1.5,llm
175
BOO
160
S8
220
290
0.5pm
1.5 Am
2.0 him
1.0 ~m, x-ray
1.5 him (CMOS)
1.0,llm
1.0 Am
1.5~1m
(300°K)
0.90
(77°K)
360
SOURCE: Reprinted, with permission, from Greiling (19873. Copyright
1987 by IEEE.
249
Representative terms from entire chapter:
oxide semiconductor
