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Getting Up to Speed The Future of Supercomputing (2005) / Chapter Skim
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Appendix D: Glossary and Acronym List
Pages 278-290

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From page 278...
... ASCI. Accelerated Strategic Computing Initiative, which provides simu lation and modeling capabilities and technologies as part of DOE/ NNSA Stockpile Stewardship Program.
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From page 279...
... Caches aim to provide the illusion of a memory as large as the main computer memory with fast performance. They succeed in doing so if memory accesses have good temporal locality and good spatial locality.
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From page 280...
... composite theoretical performance. CTP is a measure of the perfor mance of a computer that is calculated using a formula that combines various system parameters.
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From page 281...
... The memory access time depends on the memory access pattern; row access time (or row ac cess latency) is the worst-case access time, for irregular accesses.
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From page 282...
... A custom processor designed to provide significantly higher effective memory bandwidth than commodity processors normally provide. high-end computing (HEC)
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From page 283...
... A measure of delay. Memory latency is the time needed to ac cess data in memory; global communication latency is the time needed to effect a communication between two nodes through the intercon nect.
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From page 284...
... multithreaded processor. A processor that executes concurrently or si multaneously multiple threads, where the threads share computa tional resources (as distinct from a multiprocessor, where threads do not share computational resources)
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From page 285...
... NNSA. National Nuclear Security Administration, the organization within DOE that manages the Stockpile Stewardship Program that is responsible for manufacturing, maintaining, refurbishing, surveilling, and dismantling the nuclear weapons stockpile.
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From page 286...
... Parallel efficiency is an indi cation of scalability; it normally decreases as the number of proces sors increases, indicating a diminishing marginal return as more processors are applied to the solution of one problem. parallel speedup.
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From page 287...
... that involve sparse matrices, where many entries are zero. Sparse linear algebra codes use data structures that store only the nonzero matrix entries, thus saving stor
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From page 288...
... temporal locality ensures that caches can effectively capture most memory accesses, since most accesses will be to data that were accessed recently in the past and that reside in the cache.
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From page 289...
... Total cost of ownership can be significantly higher than the purchase cost, and systems with a lower purchase cost can have higher total cost of ownership.
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Key Terms

  • total cost
  • memory access
  • shared memory
  • computa tional
  • access time

  • capability computing
  • global communication
  • multiple threads
  • memory latency
  • purchase cost

  • pro cessors
  • memory accesses
  • sparse linear
  • stewardship program
  • message passing

  • multiple processors
  • stockpile stewardship
  • memory bandwidth
  • temporal locality
  • aerospace simulation

  • supercomputer built
  • computing initiative
  • access memory
  • multiple nodes
  • supercomputing centers

  • accessed soon
  • package developed
  • irregular memory
  • processing unit
  • perfor mance


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