Cutting Edge Technologies (1984) / Chapter Skim
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Ultra Large Scale Integration and Beyond
Ultra Large Scale Integration and Beyond
Pages 5-20
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From page 5... ...
The limits governing ultra large scale integration (ULSI) of 10 million to 1 billion transistors in a single chip of silicon (Si)
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From page 6... ...
And, finally, common clock skew illustrates a simple system limit depending on interconnect time delay. The totality of practical limits is described by three parameters that collectively measure the overall rate of progress of integrated electronics: (1)
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From page 7... ...
THEORETICAL LIMITS This section projects the smallest allowable dimensions for integrated structures using as relevant criteria circuit limits associated with IGFETs, polycrystalline silicon or polysilicon resistors, and interconnections. Transistors Fundamental, material, and device limits in digital electronics have been surveyed by Keyes.2 Dennard et al.3 described a constant electric field scaling theory for IGFETs.
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From page 8... ...
It is pertinent to ask, "Can we project future ULSI structures with 0.2 micron minimum feature sizes? "6 To respond on the basis of circuit scaling limits, an accurate analytical circuit model for short-channel IGFETs offers marked advantages in physical insight and computational efficiency in comparison with empirical or numerical models.
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From page 9... ...
are that the interconnect time constant or response time and voltage drop remain constant and current density increases with S Since IGFET time delay decreases as 1/S, a constant local interconnect response time assumes increasing importance.
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From page 10... ...
Although the preceding discussion of interconnect scaling applies specifically for line-to-substrate parasitic capacitance in combination with CE IGFET scaling, the salient results remain largely unaltered as one Extends the analysis to include line-to-line parasitic capacitance, CV IGFET scaling, and scaling different dimensions (e.g., interconnect thickness and field insulator thickness) at different rates.2i Overview A representative overview of the hierarchy of limits governing integrated electronics is obtained by a power-delay plot, as illustrated in Figure 2.
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From page 11... ...
PRACTICAL LIMITS Theoretical limits are based on the principles of solid-state science, whereas practical limits depend on manufacturing processes and equipment. The status of the five levels of practical limits that constrain integrated electronics can be summarized in terms of three parameters: minimum feature size, die area, and packing efficiency.
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From page 12... ...
In projecting future increases in die size, it is assumed that the historical rate established through optical lithography will continue into the early 1990s. Thereafter, the combined effects of decreasing minimum feature size and increasing die size (i.e., the combined effects of further advances in lithography)
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From page 13... ...
Although the future course of these efforts has not been projected, one may speculate on a step increase of more than 10 times in monolithic silicon substrate area, compared with the area of a single die, for future integrated systems incorporating wafer scale integration. Packing Efficiency The contribution of process, device, and circuit innovations to increasing the number of components per chip can be described by a packing efficiency parameter.
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From page 14... ...
This corresponds approximately to an increase of 100 percent annually, or 1,024 times per decade. Given that smaller minimum feature sizes and larger die sizes accounted for 8.7- and 5.7-times-per-decade increases, respectively, packing efficiency improvements must then have produced about a 21-times-perdecade increase in the number of components per chip.
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From page 15... ...
This drastic reduction of 10 times in the rate of packing efficiency improvements apparently is the result of exhausting relatively easily obtained gains in layout density that marked the first decade or so of integrated electronics. The packing efficiency contribution of about 2.1 times per decade achieved since 1972/1973 may be maintained through the 1980s and perhaps the l990s as well.
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From page 16... ...
Engine blocks and pistons are examples of specialized steel components corresponding to IGFET and bipolar integrated circuits intended for different purposes. Finally, automobiles, skyscrapers, and railroads represent the steel systems of the industrial revolution as portable computers, mainframes, and communications networks mark the silicon systems of the information revolution.
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From page 17... ...
Moreover, the history of Al, Ti, and plastic suggests a myriad of exciting future material, device, and circuit advances to propel the information revolution. The possibility that the future course of electronic materials may follow the historic patterns of structural materials implies an intriguing set of long-term analogical limits on integrated electronics.
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From page 18... ...
Theoretical limits on minimum feature size and practical limits on lithography and reliability predict a further rate reduction at that time. Nevertheless, as illustrated in Figure 6, chips incorporating several hundred million to a billion (i.e., gigascale integration, or GSI)
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From page 19... ...
J.D. Meindl et al., "Circuit Scaling Limits for Ultra-Large Scale Integration," Digest, 1981, IEEE ISSCC, pp.
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From page 20... ...
J.D. Meindl, "Theoretical, Practical and Analogical Limits in ULSI," Tech.
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