Energy-Efficient Technologies for the Dismounted Soldier (1997) / Chapter Skim
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Appendix D
Appendix D
Pages 248-262
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From page 248... ...
Using logarithmic coordinates in the power-delay plane, where the ordinate is the average power transfer during a binary transition, P and the abscissa is the delay time of the transition, to, results in a diagonal constant switching energy locus, E = Pta..
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From page 249... ...
Within these fundamental limits, the switching energy required to overcome the thermal energy of an electron, as well as the energy uncertainty resulting from its wavelike behavior, are orders of magnitude smaller than projected system limits on switching energy. (A fundamental opportunity for fisher reducing energy dissipation in binary switching operations, derived from the second law of thermodynamics, is based on conserving or recycling switching energy by maintaining constant entropy in a computing engine.
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From page 250... ...
The implications of the three semiconductor material limits are that switching energy and transit time constraints imposed by semiconductor materials per se are well below those projected for the system level, and that Si is indeed the semiconductor material of the future for low power GSI. The interconnect materials of the future are unclear but, as at the fundamental level, the time-offlight of an electromagnetic wave appears to be the most binding material limit for virtually TossTess interconnects.
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From page 251... ...
Limits on Circuits At the fourth level of the hierarchy, there are four generic circuit limits on Tow power electronics imposed by the static transfer characteristic of a logic gate, by the power-delay product or switching energy of the gate, by its propagation delay time, and finally by the response time of a global interconnect circuit (MeindI, 19951. To maintain the quintessential capability to restore binary "zero" and "one" levels virtually without error throughout a large digital system, the transfer characteristic of a complementary metal-oxide semiconductor (CMOS)
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From page 252... ...
MOSFET subthreshold swing; ,u, subthreshold channel carrier mobility, ncp, the number of gates in the critical path of the logic network; a, the network activity factor or probability that a gate will switch during a given clock cycle; b, the fraction of a clock cycle available for logic operations or the clock skew factor, Vsa`, the channel carrier saturation velocity; [, the effective channel length, and Vat /Vp the ratio of supply voltage to threshold voltage determined by performance requirements. Clearly, each MOSFET technology and each logic network configuration defines its own optimal supply voltage for Tow power operation.
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From page 253... ...
Systolic arrays exemplify such architectures (Kung, ~ 982~. The system level switching energy limit closely parallels the corresponding circuit level limit, with the distinction that capacitive loading is much greater because of the longer interconnects.
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From page 254... ...
This projection must be based on critical path models, including both a chain of random logic gates and a global interconnect circuit (Meindl, 1995~. For low power portable systems, the third generic system limit simply requires that the total power dissipation of a chip, Ps' be less than E/Tb, where Eb is the allotted battery energy for the chip and Tb is the operating interval between battery rechargings.
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From page 255... ...
FIGURE D-l Interconnect length distribution density function: interconnect length distribution density versus interconnect length. performance, which in effect moves the right boundary of the design triangle to the right, corresponding to larger propagation delay times (i.e.
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From page 256... ...
1995. Both retrospectively and prospectively, scaling down minimum feature size is the single most potent contributor to improvements in both the performance and productivity of Tow power microelectronics.
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From page 257... ...
Beyond that point, however, lie further opportunities for scaling through reduction of gate oxide thickness below the 3.0 rim tunneling limit and through SOT MOSFETs, so that at this point we do not yet see the saturation of a mature MOSFET scaling technology imposed by physical limits. Projections of trends in minimum feature size depend on understanding theoretical limits, based on relatively well understood principles of physics.
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From page 258... ...
Figure D-3 unambiguously forecasts a one billion transistor chip by 2000, a projection articulated initially in 1983 (MeindI, 19831. According to the scenario detailed in the preceding discussion and indicated by segment G in Figure D-3, in which the rates of scaling of both minimum feature size and square root of die area are reduced by 50 percent after the 0.125 ,um generation, a one trillion transistor chip will be manufactured before 2020.
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From page 259... ...
A remarkable contrast exists between the preceding treatments of theoretical and practical limits on low power GST. Projections of theoretical limits are based rather solidly on a four~dation provided by the laws of physics, as applied to particular materials, devices, circuits, arid systems resulting from 1015 1014 In E ID - Q {D · 0)
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From page 260... ...
Calculating the ratio alp = 1/np, it becomes clear that because the number of lattice sites, n, decreases as s-si2 due to scaling down MOSFET dimensions, while the probability of occupancy, p, increases as S due to scaling up doping concentration the standard deviation relative to the average number of dopant atoms increases as S3/2. The result is a larger standard deviation in the distribution of MOSFET parameters, such as threshold voltage and saturation current, as device dimensions scale down.
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From page 261... ...
Yes, we can look ahead with confidence to another decade of scaling minimum feature size, switching energy, and number of transistors per chip at the exponential rates of the past two decades. From then on, the greatest uncertainty that confronts us is what course microlithography will follow.
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From page 262... ...
Pp. 193-196 in Digest of Technical Papers, IEEE International Symposium on Low Power Electronics and Design, Monterey, California, August 11-14.
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